3336f681e3
Summary:
This change adds some verification in the IR verifier around struct path
TBAA metadata.
Other than some basic sanity checks (e.g. we get constant integers where
we expect constant integers), this checks:
- That by the time an struct access tuple `(base-type, offset)` is
"reduced" to a scalar base type, the offset is `0`. For instance, in
C++ you can't start from, say `("struct-a", 16)`, and end up with
`("int", 4)` -- by the time the base type is `"int"`, the offset
better be zero. In particular, a variant of this invariant is needed
for `llvm::getMostGenericTBAA` to be correct.
- That there are no cycles in a struct path.
- That struct type nodes have their offsets listed in an ascending
order.
- That when generating the struct access path, you eventually reach the
access type listed in the tbaa tag node.
Reviewers: dexonsmith, chandlerc, reames, mehdi_amini, manmanren
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D26438
llvm-svn: 289402
48 lines
2.0 KiB
LLVM
48 lines
2.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; FIXME: Move this to sgpr-copy.ll when this is fixed on VI.
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; Make sure that when we split an smrd instruction in order to move it to
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; the VALU, we are also moving its users to the VALU.
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; CHECK-LABEL: {{^}}split_smrd_add_worklist:
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; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
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define amdgpu_ps void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
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bb:
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%tmp = call float @llvm.SI.load.const(<16 x i8> undef, i32 96)
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%tmp1 = bitcast float %tmp to i32
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br i1 undef, label %bb2, label %bb3
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bb2: ; preds = %bb
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unreachable
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bb3: ; preds = %bb
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%tmp4 = bitcast float %tmp to i32
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%tmp5 = add i32 %tmp4, 4
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%tmp6 = sext i32 %tmp5 to i64
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%tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i64 0, i64 %tmp6
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%tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0
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%tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> <i32 1061158912, i32 1048576000>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp10 = extractelement <4 x float> %tmp9, i32 0
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%tmp12 = call i32 @llvm.SI.packf16(float %tmp10, float undef)
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%tmp13 = bitcast i32 %tmp12 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %tmp13, float undef, float undef)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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declare i32 @llvm.SI.packf16(float, float) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0, i32 1}
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!1 = !{!"const", !3}
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!2 = !{!1, !1, i64 0}
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!3 = !{!"tbaa root"}
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