7e6a73959a
Increase fp16 support to allow clspv to continue to be OpenCL compliant following the update of the OpenCL-CTS adding more testing on math functions and conversions with half. Math functions are implemented by upscaling to fp32 and using the fp32 implementation. It garantees the accuracy required for half-precision float-point by the CTS.
97 lines
3.7 KiB
C++
97 lines
3.7 KiB
C++
/*
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* Copyright (c) 2014 Advanced Micro Devices, Inc.
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* Copyright (c) 2016 Aaron Watry
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if __CLC_FPSIZE == 32
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#ifdef __CLC_SCALAR
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_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fdim(__CLC_GENTYPE x, __CLC_GENTYPE y) {
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if (__builtin_isnan(x) || __builtin_isnan(y))
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return as_float(QNANBITPATT_SP32);
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return fmax(x - y, 0.0f);
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}
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#define __CLC_FDIM_VEC(width) \
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_CLC_OVERLOAD _CLC_DEF float##width fdim(float##width x, float##width y) { \
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/* Determine if x or y is NaN. */ \
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/* Vector true is -1, i.e. all-bits-set, and NaN==NaN is false. */ \
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/* If either is NaN, then ~((x==x) & (y==y)) will be 0 (e.g. ~(-1)), as will n. */ \
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int##width n = ~((x == x) & (y == y)) & QNANBITPATT_SP32; \
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/* Calculate x-y if x>y, otherwise positive 0, again taking */ \
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/* advantage of vector true being all-bits-set. */ \
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int##width r = (x > y) & as_int##width(x - y); \
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return as_float##width(n | r); \
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}
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__CLC_FDIM_VEC(2)
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__CLC_FDIM_VEC(3)
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__CLC_FDIM_VEC(4)
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__CLC_FDIM_VEC(8)
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__CLC_FDIM_VEC(16)
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#undef __CLC_FDIM_VEC
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#endif
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#endif
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#if __CLC_FPSIZE == 64
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#ifdef __CLC_SCALAR
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_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fdim(__CLC_GENTYPE x, private __CLC_GENTYPE y) {
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long n = -(isnan(x) | isnan(y)) & QNANBITPATT_DP64;
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long r = -(x > y) & as_long(x - y);
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return as_double(n | r);
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}
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#define __CLC_FDIM_VEC(width) \
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_CLC_OVERLOAD _CLC_DEF double##width fdim(double##width x, double##width y) { \
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/* See comment in float implementation for explanation. */ \
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long##width n = ~((x == x) & (y == y)) & QNANBITPATT_DP64; \
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long##width r = (x > y) & as_long##width(x - y); \
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return as_double##width(n | r); \
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}
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__CLC_FDIM_VEC(2)
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__CLC_FDIM_VEC(3)
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__CLC_FDIM_VEC(4)
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__CLC_FDIM_VEC(8)
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__CLC_FDIM_VEC(16)
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#undef __CLC_FDIM_VEC
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#endif
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#endif
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#if __CLC_FPSIZE == 16
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#ifdef __CLC_SCALAR
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#define QNANBITPATT_FP16 ((short)0x7e00)
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_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE fdim(__CLC_GENTYPE x,
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private __CLC_GENTYPE y) {
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short n = -(isnan(x) | isnan(y)) & QNANBITPATT_FP16;
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short r = -(x > y) & as_short(x - y);
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return as_half((short)(n | r));
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}
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#define __CLC_FDIM_VEC(width) \
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_CLC_OVERLOAD _CLC_DEF half##width fdim(half##width x, half##width y) { \
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/* See comment in float implementation for explanation. */ \
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short##width n = ~((x == x) & (y == y)) & QNANBITPATT_FP16; \
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short##width r = (x > y) & as_short##width(x - y); \
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return as_half##width(n | r); \
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}
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__CLC_FDIM_VEC(2)
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__CLC_FDIM_VEC(3)
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__CLC_FDIM_VEC(4)
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__CLC_FDIM_VEC(8)
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__CLC_FDIM_VEC(16)
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#undef __CLC_FDIM_VEC
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#endif
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#endif
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