63a0a81e73
This change allows target intrinsics can have scalar args fixes [111440](https://github.com/llvm/llvm-project/issues/111440) This change will let us add scalarization for WaveReadLaneAt: https://github.com/llvm/llvm-project/pull/111010
44 lines
1.6 KiB
C++
44 lines
1.6 KiB
C++
//===- DirectXTargetTransformInfo.h - DirectX TTI ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_DIRECTX_DIRECTXTARGETTRANSFORMINFO_H
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#define LLVM_DIRECTX_DIRECTXTARGETTRANSFORMINFO_H
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#include "DirectXSubtarget.h"
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#include "DirectXTargetMachine.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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namespace llvm {
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class DirectXTTIImpl : public BasicTTIImplBase<DirectXTTIImpl> {
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using BaseT = BasicTTIImplBase<DirectXTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const DirectXSubtarget *ST;
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const DirectXTargetLowering *TLI;
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const DirectXSubtarget *getST() const { return ST; }
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const DirectXTargetLowering *getTLI() const { return TLI; }
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public:
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explicit DirectXTTIImpl(const DirectXTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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unsigned getMinVectorRegisterBitWidth() const { return 32; }
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bool isTargetIntrinsicTriviallyScalarizable(Intrinsic::ID ID) const;
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bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID,
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unsigned ScalarOpdIdx);
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};
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} // namespace llvm
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#endif // LLVM_DIRECTX_DIRECTXTARGETTRANSFORMINFO_H
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