72a218056d
This adds support for: * `muslabin32` (MIPS N32) * `muslabi64` (MIPS N64) * `muslf32` (LoongArch ILP32F/LP64F) * `muslsf` (LoongArch ILP32S/LP64S) As we start adding glibc/musl cross-compilation support for these targets in Zig, it would make our life easier if LLVM recognized these triples. I'm hoping this'll be uncontroversial since the same has already been done for `musleabi`, `musleabihf`, and `muslx32`. I intentionally left out a musl equivalent of `gnuf64` (LoongArch ILP32D/LP64D); my understanding is that Loongson ultimately settled on simply `gnu` for this much more common case, so there doesn't *seem* to be a particularly compelling reason to add a `muslf64` that's basically deprecated on arrival. Note: I don't have commit access.
128 lines
3.6 KiB
C++
128 lines
3.6 KiB
C++
//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MipsABIInfo.h"
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#include "Mips.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGenTypes/LowLevelType.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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// Note: this option is defined here to be visible from libLLVMMipsAsmParser
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// and libLLVMMipsCodeGen
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cl::opt<bool>
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EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
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cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
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cl::init(true));
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namespace {
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static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
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static const MCPhysReg Mips64IntRegs[8] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
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}
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ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
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if (IsO32())
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return ArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return ArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
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if (IsO32())
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return ArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return ArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const {
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if (IsO32())
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return CC != CallingConv::Fast ? 16 : 0;
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if (IsN32() || IsN64())
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return 0;
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llvm_unreachable("Unhandled ABI");
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}
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MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options) {
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if (Options.getABIName().starts_with("o32"))
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return MipsABIInfo::O32();
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if (Options.getABIName().starts_with("n32"))
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return MipsABIInfo::N32();
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if (Options.getABIName().starts_with("n64"))
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return MipsABIInfo::N64();
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if (TT.isABIN32())
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return MipsABIInfo::N32();
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assert(Options.getABIName().empty() && "Unknown ABI option for MIPS");
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if (TT.isMIPS64())
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return MipsABIInfo::N64();
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return MipsABIInfo::O32();
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}
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unsigned MipsABIInfo::GetStackPtr() const {
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return ArePtrs64bit() ? Mips::SP_64 : Mips::SP;
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}
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unsigned MipsABIInfo::GetFramePtr() const {
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return ArePtrs64bit() ? Mips::FP_64 : Mips::FP;
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}
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unsigned MipsABIInfo::GetBasePtr() const {
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return ArePtrs64bit() ? Mips::S7_64 : Mips::S7;
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}
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unsigned MipsABIInfo::GetGlobalPtr() const {
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return ArePtrs64bit() ? Mips::GP_64 : Mips::GP;
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}
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unsigned MipsABIInfo::GetNullPtr() const {
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return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetZeroReg() const {
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return AreGprs64bit() ? Mips::ZERO_64 : Mips::ZERO;
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}
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unsigned MipsABIInfo::GetPtrAdduOp() const {
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return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
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}
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unsigned MipsABIInfo::GetPtrAddiuOp() const {
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return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
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}
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unsigned MipsABIInfo::GetPtrSubuOp() const {
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return ArePtrs64bit() ? Mips::DSUBu : Mips::SUBu;
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}
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unsigned MipsABIInfo::GetPtrAndOp() const {
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return ArePtrs64bit() ? Mips::AND64 : Mips::AND;
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}
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unsigned MipsABIInfo::GetGPRMoveOp() const {
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return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
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}
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unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
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static const unsigned EhDataReg[] = {
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Mips::A0, Mips::A1, Mips::A2, Mips::A3
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};
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static const unsigned EhDataReg64[] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
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};
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return IsN64() ? EhDataReg64[I] : EhDataReg[I];
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}
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