Min-Yih Hsu ba65710908 [RISCV] Avoid redundant SchedRead on _TIED VPseudos (#113940) ...

_TIED and _MASK_TIED pseudos have one less operand compared to other
pseudos, thus we shouldn't attach the same number of SchedRead for these
instructions.

I don't think we have a way to (explicitly) check scheduling classes. So
I only test this patch with existing tests.

2024-10-29 10:49:35 -07:00

..

AsmParser

[RISCV][MC] Support imm symbol in parseCSRSystemRegister (#112007)

2024-10-23 16:30:35 +08:00

Disassembler

[RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)

2024-10-06 19:27:18 -07:00

GISel

[RISCV][GISEL] Legalize G_INSERT_SUBVECTOR (#108859)

2024-10-21 08:49:13 -04:00

MCA

…

MCTargetDesc

[RISCV][MC] Fix >32bit .insn Directives (#111878)

2024-10-11 12:24:54 +01:00

TargetInfo

…

CMakeLists.txt

[RISCV] Introduce VLOptimizer pass (#108640)

2024-10-11 09:45:35 -04:00

RISCV.h

[RISCV] Introduce VLOptimizer pass (#108640)

2024-10-11 09:45:35 -04:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814)

2024-09-17 18:52:55 +03:00

RISCVAsmPrinter.cpp

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

RISCVCallingConv.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVCallingConv.h

[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)

2024-09-06 09:28:33 -07:00

RISCVCallingConv.td

…

RISCVCodeGenPrepare.cpp

…

RISCVCombine.td

Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"

2024-09-20 07:01:17 -07:00

RISCVConstantPoolValue.cpp

[RISCV] Support the large code model. (#70308)

2024-09-09 09:15:07 +08:00

RISCVConstantPoolValue.h

[RISCV] Support the large code model. (#70308)

2024-09-09 09:15:07 +08:00

RISCVDeadRegisterDefinitions.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (#113981)

2024-10-28 22:37:47 -07:00

RISCVFeatures.td

[RISCV] Remove trailing whitespace. NFC

2024-10-29 10:09:28 -07:00

RISCVFrameLowering.cpp

[RISC-V] Fix check of minimum vlen. (#114055)

2024-10-29 17:30:30 +00:00

RISCVFrameLowering.h

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

RISCVGatherScatterLowering.cpp

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

RISCVGISel.td

[RISCV][GISel] Correct RORIW patterns.

2024-10-17 09:32:45 -07:00

RISCVIndirectBranchTracking.cpp

…

RISCVInsertReadWriteCSR.cpp

…

RISCVInsertVSETVLI.cpp

[RISCV][NFC] Remove the unused RISCV_COALESCE_VSETVLI_NAME (#111536)

2024-10-08 19:53:34 +02:00

RISCVInsertWriteVXRM.cpp

…

RISCVInstrFormats.td

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022)

2024-10-08 14:09:07 +01:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISEL] Fix operand on RISCV::G_VMV_V_V_VL

2024-10-21 06:58:12 -07:00

RISCVInstrInfo.cpp

[RISCV] Remove support for pre-RA vsetvli insertion (#110796)

2024-10-28 11:31:18 +00:00

RISCVInstrInfo.h

[RISCV][VLOPT] Allow propagation even when VL isn't VLMAX (#112228)

2024-10-16 14:58:00 -04:00

RISCVInstrInfo.td

[RISCV] Add Smrnmi extension (#111668)

2024-10-25 18:41:21 +11:00

RISCVInstrInfoA.td

…

RISCVInstrInfoC.td

[RISCV] Convert C_ADDI_NOP to C_NOP in the assembler. (#112314)

2024-10-16 09:47:06 -07:00

RISCVInstrInfoD.td

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

RISCVInstrInfoF.td

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

RISCVInstrInfoM.td

…

RISCVInstrInfoSFB.td

…

RISCVInstrInfoV.td

[RISCV] Avoid redundant SchedRead on _TIED VPseudos (#113940)

2024-10-29 10:49:35 -07:00

RISCVInstrInfoVPseudos.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)

2024-10-28 09:37:54 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Add explicit XLenVT cast to vector load/store patterns.

2024-09-23 16:02:58 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Lower vector_reverse for zvfhmin/zvfbfmin (#110218)

2024-10-02 14:25:15 +08:00

RISCVInstrInfoXCV.td

[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (#100684)

2024-10-01 11:22:02 +10:00

RISCVInstrInfoXSf.td

[RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (#111630)

2024-10-14 21:10:55 -07:00

RISCVInstrInfoXTHead.td

[RISCV] Use THShift_ri class instead of RVBShift_ri for TH_TST instruction. NFC

2024-10-05 11:52:10 -07:00

RISCVInstrInfoXVentana.td

…

RISCVInstrInfoXwch.td

…

RISCVInstrInfoZa.td

…

RISCVInstrInfoZalasr.td

…

RISCVInstrInfoZb.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZc.td

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

RISCVInstrInfoZcmop.td

…

RISCVInstrInfoZfa.td

[RISCV] Only disassemble fcvtmod.w.d if the rounding mode is rtz. (#111308)

2024-10-06 19:27:18 -07:00

RISCVInstrInfoZfbfmin.td

[RISCV] Remove RISCVISD::FP_ROUND_BF16.

2024-09-03 20:18:01 -07:00

RISCVInstrInfoZfh.td

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

RISCVInstrInfoZicbo.td

…

RISCVInstrInfoZicfiss.td

…

RISCVInstrInfoZicond.td

…

RISCVInstrInfoZimop.td

…

RISCVInstrInfoZk.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279)

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZvfbf.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

2024-09-05 15:27:48 +08:00

RISCVInstrInfoZvk.td

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

2024-09-05 15:27:48 +08:00

RISCVISelDAGToDAG.cpp

[RISCV][ISel] Select binvi for pattern icmp eq/ne X, pow2 (#110957)

2024-10-03 15:13:02 +08:00

RISCVISelDAGToDAG.h

[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284)

2024-09-11 21:13:26 -07:00

RISCVISelLowering.cpp

[RISCV] Lower @llvm.experimental.vector.compress for zvfhmin/zvfbfmin (#113770)

2024-10-28 09:37:06 +00:00

RISCVISelLowering.h

[RISCV] Add lowering for @llvm.experimental.vector.compress (#113291)

2024-10-23 14:22:32 +08:00

RISCVLandingPadSetup.cpp

…

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

…

RISCVMacroFusion.td

…

RISCVMakeCompressible.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVMergeBaseOffset.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

RISCVMoveMerger.cpp

…

RISCVOptWInstrs.cpp

…

RISCVPostRAExpandPseudoInsts.cpp

…

RISCVProcessors.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814)

2024-09-17 18:52:55 +03:00

RISCVProfiles.td

[RISCV] Mark RVB23U64 and RVB23S64 as non-experimental (#113918)

2024-10-29 07:57:34 +00:00

RISCVPushPopOptimizer.cpp

…

RISCVRedundantCopyElimination.cpp

…

RISCVRegisterInfo.cpp

[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)

2024-09-30 23:52:35 -07:00

RISCVRegisterInfo.h

[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)

2024-09-30 23:52:35 -07:00

RISCVRegisterInfo.td

[RISCV][ISel] Ensure 'in X' Constraints prevent X0 (#112563)

2024-10-18 22:33:35 +01:00

RISCVSchedRocket.td

…

RISCVSchedSiFive7.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)

2024-10-28 09:37:54 -07:00

RISCVSchedSiFiveP400.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)

2024-10-28 09:37:54 -07:00

RISCVSchedSiFiveP600.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)

2024-10-28 09:37:54 -07:00

RISCVSchedSyntacoreSCR1.td

…

RISCVSchedSyntacoreSCR7.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814)

2024-09-17 18:52:55 +03:00

RISCVSchedSyntacoreSCR345.td

…

RISCVSchedule.td

…

RISCVScheduleV.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009)

2024-10-28 09:37:54 -07:00

RISCVScheduleXSf.td

…

RISCVScheduleZb.td

…

RISCVScheduleZvk.td

…

RISCVSchedXiangShanNanHu.td

…

RISCVSubtarget.cpp

…

RISCVSubtarget.h

[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)

2024-09-16 09:48:25 +02:00

RISCVSystemOperands.td

…

RISCVTargetMachine.cpp

[RISCV] Remove support for pre-RA vsetvli insertion (#110796)

2024-10-28 11:31:18 +00:00

RISCVTargetMachine.h

…

RISCVTargetObjectFile.cpp

[RISCV] Support the large code model. (#70308)

2024-09-09 09:15:07 +08:00

RISCVTargetObjectFile.h

…

RISCVTargetTransformInfo.cpp

[RISCV][TTI] Recognize CONCAT_VECTORS if a shufflevector mask is multiple insert subvector. (#111459)

2024-10-18 20:16:56 +07:00

RISCVTargetTransformInfo.h

[SLP]Initial support for interleaved loads

2024-10-14 09:12:33 -04:00

RISCVVectorPeephole.cpp

[RISCV][VLOPT] Allow propagation even when VL isn't VLMAX (#112228)

2024-10-16 14:58:00 -04:00

RISCVVLOptimizer.cpp

[RISCV] Fix gcc -Wparentheses warning [NFC]

2024-10-17 08:00:31 +02:00

RISCVZacasABIFix.cpp

[RISCV] Add additional fence for amocas when required by recent ABI change (#101023)

2024-09-19 13:39:56 +01:00