8d49ce1764
This hooks up G_INTRINSIC_LLRINT instructions, very similar to the lrint nodes that already exist. On AArch64 they are treated the same as lrint with the default return types.
81 lines
2.2 KiB
LLVM
81 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s
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define i32 @testmsws(float %x) {
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; CHECK-LABEL: testmsws:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: frintx s0, s0
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; CHECK-NEXT: fcvtzs x0, s0
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; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.f32(float %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsxs(float %x) {
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; CHECK-LABEL: testmsxs:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: frintx s0, s0
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; CHECK-NEXT: fcvtzs x0, s0
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.f32(float %x)
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ret i64 %0
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}
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define i32 @testmswd(double %x) {
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; CHECK-LABEL: testmswd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: frintx d0, d0
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; CHECK-NEXT: fcvtzs x0, d0
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; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.f64(double %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsxd(double %x) {
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; CHECK-LABEL: testmsxd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: frintx d0, d0
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; CHECK-NEXT: fcvtzs x0, d0
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.f64(double %x)
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ret i64 %0
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}
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define i32 @testmswl(fp128 %x) {
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; CHECK-LABEL: testmswl:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: bl llrintl
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; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsll(fp128 %x) {
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; CHECK-LABEL: testmsll:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: b llrintl
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entry:
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%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
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ret i64 %0
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}
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declare i64 @llvm.llrint.f32(float) nounwind readnone
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declare i64 @llvm.llrint.f64(double) nounwind readnone
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declare i64 @llvm.llrint.f128(fp128) nounwind readnone
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