c3260c65e8
This adds the `llvm.sincos` intrinsic, legalization, and lowering.
The `llvm.sincos` intrinsic takes a floating-point value and returns
both the sine and cosine (as a struct).
```
declare { float, float } @llvm.sincos.f32(float %Val)
declare { double, double } @llvm.sincos.f64(double %Val)
declare { x86_fp80, x86_fp80 } @llvm.sincos.f80(x86_fp80 %Val)
declare { fp128, fp128 } @llvm.sincos.f128(fp128 %Val)
declare { ppc_fp128, ppc_fp128 } @llvm.sincos.ppcf128(ppc_fp128 %Val)
declare { <4 x float>, <4 x float> } @llvm.sincos.v4f32(<4 x float> %Val)
```
The lowering is built on top of the existing FSINCOS ISD node, with
additional type legalization to allow for f16, f128, and vector values.
102 lines
4.1 KiB
LLVM
102 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=aarch64-gnu-linux < %s | FileCheck -check-prefixes=CHECK %s
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define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
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; CHECK-LABEL: test_frexp_v2f16_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov h1, v0.h[1]
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; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: add x0, sp, #36
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; CHECK-NEXT: add x19, sp, #36
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; CHECK-NEXT: fcvt s0, h1
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: add x0, sp, #32
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; CHECK-NEXT: fcvt s1, h1
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; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: fmov s0, s1
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: fcvt h2, s0
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; CHECK-NEXT: add x0, sp, #40
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; CHECK-NEXT: mov h1, v1.h[2]
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; CHECK-NEXT: fcvt s0, h1
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: mov v2.h[1], v1.h[0]
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; CHECK-NEXT: str q2, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: ldr q1, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: fcvt h2, s0
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; CHECK-NEXT: add x0, sp, #44
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; CHECK-NEXT: mov h1, v1.h[3]
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; CHECK-NEXT: fcvt s0, h1
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: mov v1.h[2], v2.h[0]
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; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: fcvt h2, s0
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; CHECK-NEXT: ldr s1, [sp, #32]
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; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: ld1 { v1.s }[1], [x19]
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; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
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; CHECK-NEXT: mov v0.h[3], v2.h[0]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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%result = call { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half> %a)
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ret { <2 x half>, <2 x i32> } %result
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}
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define { <3 x float>, <3 x i32> } @test_frexp_v3f16_v3i32(<3 x float> %a) {
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; CHECK-LABEL: test_frexp_v3f16_v3i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #80
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; CHECK-NEXT: str x30, [sp, #48] // 8-byte Folded Spill
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; CHECK-NEXT: stp x20, x19, [sp, #64] // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 80
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: .cfi_offset w30, -32
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; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov s0, v0.s[1]
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; CHECK-NEXT: add x0, sp, #56
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; CHECK-NEXT: add x19, sp, #56
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: add x0, sp, #44
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; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: add x0, sp, #60
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; CHECK-NEXT: add x20, sp, #60
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; CHECK-NEXT: mov v0.s[1], v1.s[0]
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; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: mov s0, v0.s[2]
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; CHECK-NEXT: bl frexpf
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; CHECK-NEXT: ldr s1, [sp, #44]
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; CHECK-NEXT: ldr q2, [sp] // 16-byte Folded Reload
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; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
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; CHECK-NEXT: ldr x30, [sp, #48] // 8-byte Folded Reload
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; CHECK-NEXT: ld1 { v1.s }[1], [x19]
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; CHECK-NEXT: mov v2.s[2], v0.s[0]
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; CHECK-NEXT: ld1 { v1.s }[2], [x20]
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; CHECK-NEXT: ldp x20, x19, [sp, #64] // 16-byte Folded Reload
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: add sp, sp, #80
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; CHECK-NEXT: ret
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%result = call { <3 x float>, <3 x i32> } @llvm.frexp.v3float.v3i32(<3 x float> %a)
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ret { <3 x float>, <3 x i32> } %result
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}
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