5feb32ba92
This patch is intended to be the first of a series with end goal to adapt atomic optimizer pass to support i64 and f64 operations (along with removing all unnecessary bitcasts). This legalizes 64 bit readlane, writelane and readfirstlane ops pre-ISel --------- Co-authored-by: vikramRH <vikhegde@amd.com>
71 lines
2.7 KiB
LLVM
71 lines
2.7 KiB
LLVM
; RUN: llc -stop-after=amdgpu-isel -mtriple=amdgcn-- -mcpu=gfx1100 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=CHECK,ISEL %s
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; RUN: not --crash llc -mtriple=amdgcn--amdhsa -mcpu=1100 -verify-machineinstrs < %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
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; FIXME: Merge these tests with existing lane op tests (llvm.amdgcn.readlane.ll, llvm.amdgcn.writelane.ll ...) once the crash is fixed.
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; CHECK-LABEL: name: basic_readfirstlane_i64
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; CHECK: [[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL_ANCHOR
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; ISEL: CONVERGENCECTRL_GLUE [[TOKEN]]
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; ISEL: {{.*}} = V_READFIRSTLANE_B32 {{.*}}, implicit [[TOKEN]]
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; ISEL: CONVERGENCECTRL_GLUE [[TOKEN]]
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; ISEL: {{.*}} = V_READFIRSTLANE_B32 {{.*}}, implicit [[TOKEN]]
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define i64 @basic_readfirstlane_i64(i64 %src, i1 %cond) #0 {
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entry:
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%t = call token @llvm.experimental.convergence.anchor()
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%x = add i64 %src, 1
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br i1 %cond, label %then, label %else
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then:
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; CHECK-ERROR: Cannot mix controlled and uncontrolled convergence in the same function.
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; CHECK-ERROR: V_READFIRSTLANE_B32
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%r = call i64 @llvm.amdgcn.readfirstlane.i64(i64 %x) [ "convergencectrl"(token %t) ]
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br label %else
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else:
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%p = phi i64 [%r, %then], [%x, %entry]
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ret i64 %p
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}
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; CHECK-LABEL: name: basic_readlane_i64
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; CHECK: [[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL_ANCHOR
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; ISEL: CONVERGENCECTRL_GLUE [[TOKEN]]
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; ISEL: {{.*}} = V_READLANE_B32 {{.*}}, implicit [[TOKEN]]
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; ISEL: CONVERGENCECTRL_GLUE [[TOKEN]]
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; ISEL: {{.*}} = V_READLANE_B32 {{.*}}, implicit [[TOKEN]]
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define i64 @basic_readlane_i64(i64 %src, i32 %lane, i1 %cond) #0 {
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entry:
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%t = call token @llvm.experimental.convergence.anchor()
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%x = add i64 %src, 1
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br i1 %cond, label %then, label %else
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then:
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%r = call i64 @llvm.amdgcn.readlane.i64(i64 %x, i32 %lane) [ "convergencectrl"(token %t) ]
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br label %else
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else:
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%p = phi i64 [%r, %then], [%x, %entry]
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ret i64 %p
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}
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; CHECK-LABEL: name: basic_writelane_i64
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; CHECK: [[TOKEN:%[0-9]+]]{{[^ ]*}} = CONVERGENCECTRL_ANCHOR
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; ISEL: CONVERGENCECTRL_GLUE [[TOKEN]]
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; ISEL: {{.*}} = V_WRITELANE_B32 {{.*}}, implicit [[TOKEN]]
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; ISEL: CONVERGENCECTRL_GLUE [[TOKEN]]
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; ISEL: {{.*}} = V_WRITELANE_B32 {{.*}}, implicit [[TOKEN]]
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define i64 @basic_writelane_i64(i64 %src, i1 %cond, i32 %lane, ptr addrspace(1) %out) #0 {
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entry:
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%old = load i64, ptr addrspace(1) %out
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%t = call token @llvm.experimental.convergence.anchor()
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%x = add i64 %src, 1
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br i1 %cond, label %then, label %else
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then:
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%r = call i64 @llvm.amdgcn.writelane.i64(i64 %x, i32 %lane, i64 %old) [ "convergencectrl"(token %t) ]
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br label %else
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else:
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%p = phi i64 [%r, %then], [%x, %entry]
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ret i64 %p
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}
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