229e118559
For targets that support xnack replay feature (gfx8+), the multi-dword scalar loads shouldn't clobber any register that holds the src address. The constrained version of the scalar loads have the early clobber flag attached to the dst operand to restrict RA from re-allocating any of the src regs for its dst operand.
40 lines
1.7 KiB
LLVM
40 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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define amdgpu_kernel void @copy_to_scc(ptr addrspace(1) %out, ptr addrspace(1) %in, ptr addrspace(4) %addrSrc) {
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; GCN-LABEL: copy_to_scc:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x34
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_load_dword v0, off, s[4:7], 0 offset:252
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_load_dword s0, s[6:7], 0x0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_lg_u32 s0, 0
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; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0
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; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], vcc
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; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec
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; GCN-NEXT: s_cselect_b32 s0, 2, 3
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: global_store_dword v1, v0, s[4:5]
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; GCN-NEXT: s_endpgm
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entry: ; preds = %1009
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%0 = load i32, ptr addrspace(1) %in, align 4
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%1 = load ptr addrspace(8), ptr addrspace(4) %addrSrc, align 16
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%2 = icmp ne i32 %0, 0
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%3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) %1, i32 252, i32 0, i32 0)
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%4 = icmp ne i32 %3, 0
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%5 = xor i1 %2, %4
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%result = select i1 %5, i32 2, i32 3
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8), i32, i32, i32 immarg)
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