53d33d3ba5
When we check if an access can be skipped, there is a case that an inter-procedural interference access exists after a dominant write. Currently we rely on `AAInterFnReachability` to tell if the access can be reachable. If it is not, we can safely skip the access. However, it is based on an assumption that the AA exists. It is possible that the AA doesn't exist. In this case, we can't safely assume the acess can be skipped because we have to assume the access can reach. This can happen when `AAInterFnReachability` is not in the allowed AA list when creating the attributor, such as AMDGPUAttributor. Co-authored-by: Mark de Wever <koraq@xs4all.nl>
74 lines
2.8 KiB
LLVM
74 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s -o - | FileCheck %s
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@g_fn = addrspace(1) global ptr null
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;.
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; CHECK: @g_fn = addrspace(1) global ptr null
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;.
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define void @set_fn(ptr %fn) {
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; CHECK-LABEL: define {{[^@]+}}@set_fn
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; CHECK-SAME: (ptr [[FN:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store ptr [[FN]], ptr addrspace(1) @g_fn, align 8
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; CHECK-NEXT: ret void
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;
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entry:
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store ptr %fn, ptr addrspace(1) @g_fn
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ret void
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}
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define void @get_fn(ptr %fn) {
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; CHECK-LABEL: define {{[^@]+}}@get_fn
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; CHECK-SAME: (ptr [[FN:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(1) @g_fn, align 8
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; CHECK-NEXT: store ptr [[LOAD]], ptr [[FN]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%load = load ptr, ptr addrspace(1) @g_fn
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store ptr %load, ptr %fn
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ret void
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}
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define void @foo() {
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; CHECK-LABEL: define {{[^@]+}}@foo
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; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[FN:%.*]] = alloca ptr, align 8, addrspace(5)
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; CHECK-NEXT: store ptr null, ptr addrspace(5) [[FN]], align 8
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; CHECK-NEXT: [[FN_CAST:%.*]] = addrspacecast ptr addrspace(5) [[FN]] to ptr
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; CHECK-NEXT: call void @get_fn(ptr [[FN_CAST]])
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; CHECK-NEXT: [[LOAD:%.*]] = load ptr, ptr addrspace(5) [[FN]], align 8
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; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne ptr [[LOAD]], null
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; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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; CHECK: if.then:
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; CHECK-NEXT: [[LOAD_1:%.*]] = load ptr, ptr addrspace(5) [[FN]], align 8
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; CHECK-NEXT: call void [[LOAD_1]]()
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; CHECK-NEXT: br label [[IF_END]]
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; CHECK: if.end:
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; CHECK-NEXT: ret void
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;
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entry:
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%fn = alloca ptr, addrspace(5)
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store ptr null, ptr addrspace(5) %fn
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%fn.cast = addrspacecast ptr addrspace(5) %fn to ptr
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call void @get_fn(ptr %fn.cast)
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%load = load ptr, ptr addrspace(5) %fn
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%tobool = icmp ne ptr %load, null
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br i1 %tobool, label %if.then, label %if.end
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if.then:
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%load.1 = load ptr, ptr addrspace(5) %fn
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call void %load.1()
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br label %if.end
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if.end:
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ret void
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}
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;.
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; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR1]] = { "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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;.
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