d880f5a4c9
This patch removes the conservative uniformity check in the indirect call specialization callback, as whether the function pointer is uniform doesn't matter too much. Instead, we add an argument to control specialization.
114 lines
5.6 KiB
LLVM
114 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck --check-prefixes=CHECK,OW %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes='amdgpu-attributor<closed-world>' %s | FileCheck --check-prefixes=CHECK,CW %s
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; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes='amdgpu-attributor<closed-world>' -amdgpu-indirect-call-specialization-threshold=0 %s | FileCheck --check-prefixes=CHECK,NO %s
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target datalayout = "A5"
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@G = global i32 0, align 4
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;.
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; CHECK: @G = global i32 0, align 4
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;.
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define void @bar1() {
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; CHECK-LABEL: define {{[^@]+}}@bar1
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; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store i32 1, ptr @G, align 4
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; CHECK-NEXT: ret void
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;
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entry:
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store i32 1, ptr @G, align 4
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ret void
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}
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define void @bar2() {
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; CHECK-LABEL: define {{[^@]+}}@bar2
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; CHECK-SAME: () #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: store i32 2, ptr @G, align 4
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; CHECK-NEXT: ret void
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;
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entry:
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store i32 2, ptr @G, align 4
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ret void
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}
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define ptr @helper1() {
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; CHECK-LABEL: define {{[^@]+}}@helper1
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; CHECK-SAME: () #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret ptr @bar1
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;
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entry:
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ret ptr @bar1
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}
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define ptr @helper2() {
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; CHECK-LABEL: define {{[^@]+}}@helper2
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; CHECK-SAME: () #[[ATTR0]] {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: ret ptr @bar2
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;
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entry:
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ret ptr @bar2
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}
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define amdgpu_kernel void @foo(ptr noundef %fp) {
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; OW-LABEL: define {{[^@]+}}@foo
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; OW-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR1:[0-9]+]] {
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; OW-NEXT: entry:
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; OW-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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; OW-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8
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; OW-NEXT: call void [[FP]]()
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; OW-NEXT: ret void
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;
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; CW-LABEL: define {{[^@]+}}@foo
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; CW-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR1:[0-9]+]] {
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; CW-NEXT: entry:
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; CW-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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; CW-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8
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; CW-NEXT: [[TMP0:%.*]] = icmp eq ptr [[FP]], @bar1
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; CW-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label [[TMP2:%.*]]
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; CW: 1:
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; CW-NEXT: call void @bar1()
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; CW-NEXT: br label [[TMP5:%.*]]
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; CW: 2:
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; CW-NEXT: br i1 true, label [[TMP3:%.*]], label [[TMP4:%.*]]
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; CW: 3:
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; CW-NEXT: call void @bar2()
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; CW-NEXT: br label [[TMP5]]
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; CW: 4:
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; CW-NEXT: unreachable
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; CW: 5:
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; CW-NEXT: ret void
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;
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; NO-LABEL: define {{[^@]+}}@foo
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; NO-SAME: (ptr noundef [[FP:%.*]]) #[[ATTR1:[0-9]+]] {
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; NO-NEXT: entry:
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; NO-NEXT: [[FP_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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; NO-NEXT: store ptr [[FP]], ptr addrspace(5) [[FP_ADDR]], align 8
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; NO-NEXT: call void [[FP]](), !callees [[META0:![0-9]+]]
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; NO-NEXT: ret void
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;
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entry:
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%fp.addr = alloca ptr, addrspace(5)
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store ptr %fp, ptr addrspace(5) %fp.addr
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%load = load ptr, ptr addrspace(5) %fp.addr
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call void %load()
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ret void
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}
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;.
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; NO: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; NO: attributes #[[ATTR1]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
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;.
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; OW: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; OW: attributes #[[ATTR1]] = { "uniform-work-group-size"="false" }
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;.
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; CW: attributes #[[ATTR0]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; CW: attributes #[[ATTR1]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
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;.
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; NO: [[META0]] = !{ptr @bar1, ptr @bar2}
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;.
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