229e118559
For targets that support xnack replay feature (gfx8+), the multi-dword scalar loads shouldn't clobber any register that holds the src address. The constrained version of the scalar loads have the early clobber flag attached to the dst operand to restrict RA from re-allocating any of the src regs for its dst operand.
254 lines
9.9 KiB
LLVM
254 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -global-isel -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GISEL %s
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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define amdgpu_kernel void @v_pack_b32_v2f16(ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {
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; GCN-LABEL: v_pack_b32_v2f16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_f16_e32 v0, 2.0, v1
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; GCN-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GCN-NEXT: v_pack_b32_f16 v0, v0, v1
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use v0
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_endpgm
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;
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; GISEL-LABEL: v_pack_b32_v2f16:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: v_add_f16_e32 v0, 2.0, v1
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; GISEL-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; use v0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds half, ptr addrspace(1) %in0, i64 %tid.ext
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%in1.gep = getelementptr inbounds half, ptr addrspace(1) %in1, i64 %tid.ext
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%v0 = load volatile half, ptr addrspace(1) %in0.gep
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%v1 = load volatile half, ptr addrspace(1) %in1.gep
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%v0.add = fadd half %v0, 2.0
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%v1.add = fadd half %v1, 2.0
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%vec.0 = insertelement <2 x half> undef, half %v0.add, i32 0
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%vec.1 = insertelement <2 x half> %vec.0, half %v1.add, i32 1
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%vec.i32 = bitcast <2 x half> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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define amdgpu_kernel void @v_pack_b32_v2f16_sub(ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {
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; GCN-LABEL: v_pack_b32_v2f16_sub:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_subrev_f16_e32 v0, 2.0, v1
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; GCN-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GCN-NEXT: v_pack_b32_f16 v0, v0, v1
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use v0
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_endpgm
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;
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; GISEL-LABEL: v_pack_b32_v2f16_sub:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: v_subrev_f16_e32 v0, 2.0, v1
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; GISEL-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; use v0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds half, ptr addrspace(1) %in0, i64 %tid.ext
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%in1.gep = getelementptr inbounds half, ptr addrspace(1) %in1, i64 %tid.ext
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%v0 = load volatile half, ptr addrspace(1) %in0.gep
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%v1 = load volatile half, ptr addrspace(1) %in1.gep
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%v0.add = fsub half %v0, 2.0
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%v1.add = fadd half %v1, 2.0
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%vec.0 = insertelement <2 x half> undef, half %v0.add, i32 0
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%vec.1 = insertelement <2 x half> %vec.0, half %v1.add, i32 1
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%vec.i32 = bitcast <2 x half> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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define amdgpu_kernel void @fptrunc(
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; GCN-LABEL: fptrunc:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_mov_b32 s3, 0x31016000
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; GCN-NEXT: s_mov_b32 s10, s2
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; GCN-NEXT: s_mov_b32 s11, s3
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 s8, s6
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; GCN-NEXT: s_mov_b32 s9, s7
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; GCN-NEXT: s_mov_b32 s0, s4
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; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
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; GCN-NEXT: s_mov_b32 s1, s5
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_cvt_f16_f32_e32 v1, v1
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; GCN-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GCN-NEXT: v_pack_b32_f16 v0, v0, v1
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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;
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; GISEL-LABEL: fptrunc:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
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; GISEL-NEXT: s_mov_b32 s6, -1
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; GISEL-NEXT: s_mov_b32 s7, 0x31016000
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; GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-NEXT: v_cvt_f16_f32_e32 v0, s0
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; GISEL-NEXT: v_cvt_f16_f32_e32 v1, s1
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; GISEL-NEXT: v_pack_b32_f16 v0, v0, v1
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; GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GISEL-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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%a.val = load <2 x float>, ptr addrspace(1) %a
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%r.val = fptrunc <2 x float> %a.val to <2 x half>
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store <2 x half> %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @v_pack_b32.fabs(ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {
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; GCN-LABEL: v_pack_b32.fabs:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_f16_e32 v0, 2.0, v1
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; GCN-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GCN-NEXT: v_pack_b32_f16 v0, |v0|, |v1|
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use v0
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_endpgm
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;
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; GISEL-LABEL: v_pack_b32.fabs:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: v_add_f16_e32 v0, 2.0, v1
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; GISEL-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GISEL-NEXT: v_pack_b32_f16 v0, |v0|, |v1|
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; use v0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds half, ptr addrspace(1) %in0, i64 %tid.ext
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%in1.gep = getelementptr inbounds half, ptr addrspace(1) %in1, i64 %tid.ext
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%v0 = load volatile half, ptr addrspace(1) %in0.gep
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%v1 = load volatile half, ptr addrspace(1) %in1.gep
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%v0.add = fadd half %v0, 2.0
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%v1.add = fadd half %v1, 2.0
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%v0.fabs = call half @llvm.fabs.f16(half %v0.add)
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%v1.fabs = call half @llvm.fabs.f16(half %v1.add)
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%vec.0 = insertelement <2 x half> undef, half %v0.fabs, i32 0
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%vec.1 = insertelement <2 x half> %vec.0, half %v1.fabs, i32 1
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%vec.i32 = bitcast <2 x half> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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define amdgpu_kernel void @v_pack_b32.fneg(ptr addrspace(1) %in0, ptr addrspace(1) %in1) #0 {
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; GCN-LABEL: v_pack_b32.fneg:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_f16_e32 v0, 2.0, v1
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; GCN-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GCN-NEXT: v_pack_b32_f16 v0, -v0, -v1
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ; use v0
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_endpgm
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;
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; GISEL-LABEL: v_pack_b32.fneg:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x24
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; GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
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; GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-NEXT: global_load_ushort v1, v0, s[4:5] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: global_load_ushort v2, v0, s[6:7] glc dlc
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: v_add_f16_e32 v0, 2.0, v1
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; GISEL-NEXT: v_add_f16_e32 v1, 2.0, v2
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; GISEL-NEXT: v_pack_b32_f16 v0, -v0, -v1
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; GISEL-NEXT: ;;#ASMSTART
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; GISEL-NEXT: ; use v0
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; GISEL-NEXT: ;;#ASMEND
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; GISEL-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%in0.gep = getelementptr inbounds half, ptr addrspace(1) %in0, i64 %tid.ext
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%in1.gep = getelementptr inbounds half, ptr addrspace(1) %in1, i64 %tid.ext
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%v0 = load volatile half, ptr addrspace(1) %in0.gep
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%v1 = load volatile half, ptr addrspace(1) %in1.gep
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%v0.add = fadd half %v0, 2.0
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%v1.add = fadd half %v1, 2.0
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%v0.fneg = fsub half -0.0, %v0.add
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%v1.fneg = fsub half -0.0, %v1.add
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%vec.0 = insertelement <2 x half> undef, half %v0.fneg, i32 0
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%vec.1 = insertelement <2 x half> %vec.0, half %v1.fneg, i32 1
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%vec.i32 = bitcast <2 x half> %vec.1 to i32
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call void asm sideeffect "; use $0", "v"(i32 %vec.i32) #0
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ret void
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}
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declare half @llvm.fabs.f16(half) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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