86627149f6
Any SGPR read by a VALU can potentially obscure SALU writes to the same register. Insert s_wait_alu instructions to mitigate the hazard on affected paths. Compute a global cache of SGPRs with any VALU reads and use this to avoid inserting mitigation for SGPRs never accessed by VALUs. To avoid excessive search when compile time is priority implement secondary mode where all SALU writes are mitigated. Co-authored-by: Shilei Tian <shilei.tian@amd.com>
115 lines
5.1 KiB
LLVM
115 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-TRUE16 %s
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; RUN: llc -march=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-FAKE16 %s
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define half @swap(half %a, half %b, i32 %i) {
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; GFX11-TRUE16-LABEL: swap:
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; GFX11-TRUE16: ; %bb.0: ; %entry
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
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; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
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; GFX11-TRUE16-NEXT: .LBB0_1: ; %loop
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; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
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; GFX11-TRUE16-NEXT: v_swap_b16 v0.l, v0.h
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; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
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; GFX11-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
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; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB0_1
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; GFX11-TRUE16-NEXT: ; %bb.2: ; %ret
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; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-FAKE16-LABEL: swap:
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; GFX11-FAKE16: ; %bb.0: ; %entry
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
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; GFX11-FAKE16-NEXT: .LBB0_1: ; %loop
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; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
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; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, -1, v2
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; GFX11-FAKE16-NEXT: v_swap_b32 v1, v0
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; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
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; GFX11-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
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; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB0_1
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; GFX11-FAKE16-NEXT: ; %bb.2: ; %ret
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; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1
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; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: swap:
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; GFX12-TRUE16: ; %bb.0: ; %entry
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l
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; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
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; GFX12-TRUE16-NEXT: s_mov_b32 s0, 0
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; GFX12-TRUE16-NEXT: .LBB0_1: ; %loop
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; GFX12-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX12-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
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; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
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; GFX12-TRUE16-NEXT: v_swap_b16 v0.l, v0.h
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; GFX12-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
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; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
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; GFX12-TRUE16-NEXT: s_or_b32 s0, vcc_lo, s0
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; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
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; GFX12-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
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; GFX12-TRUE16-NEXT: s_cbranch_execnz .LBB0_1
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; GFX12-TRUE16-NEXT: ; %bb.2: ; %ret
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; GFX12-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GFX12-TRUE16-NEXT: s_wait_alu 0xfffe
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-FAKE16-LABEL: swap:
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; GFX12-FAKE16: ; %bb.0: ; %entry
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; GFX12-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_expcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
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; GFX12-FAKE16-NEXT: .LBB0_1: ; %loop
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; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, -1, v2
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; GFX12-FAKE16-NEXT: v_swap_b32 v1, v0
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; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
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; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
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; GFX12-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
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; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
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; GFX12-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
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; GFX12-FAKE16-NEXT: s_cbranch_execnz .LBB0_1
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; GFX12-FAKE16-NEXT: ; %bb.2: ; %ret
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; GFX12-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
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; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v1
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; GFX12-FAKE16-NEXT: s_wait_alu 0xfffe
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; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
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entry:
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br label %loop
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loop:
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%x = phi half [%a, %entry], [%y, %loop]
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%y = phi half [%b, %entry], [%x, %loop]
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%i2 = phi i32 [%i, %entry], [%i3, %loop]
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%i3 = sub i32 %i2, 1
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%cmp = icmp eq i32 %i3, 0
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br i1 %cmp, label %ret, label %loop
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ret:
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ret half %x
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}
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