3b16630c26
This PR depends on https://github.com/llvm/llvm-project/pull/90260 We changed the order in which functions are outlined in Machine Outliner. The formula for priority is found via a black-box Bayesian optimization toolbox. Using this formula for sorting consistently reduces the uncompressed size of large real-world mobile apps. We also ran a few benchmarks using LLVM test suites, and showed that sorting by priority consistently reduces the text segment size. |run (CTMark/) |baseline (1)|priority (2)|diff (1 -> 2)| |----------------|------------|------------|-------------| |lencod |349624 |349264 |-0.1030% | |SPASS |219672 |219480 |-0.0874% | |kc |271956 |251200 |-7.6321% | |sqlite3 |223920 |223708 |-0.0947% | |7zip-benchmark |405364 |402624 |-0.6759% | |bullet |139820 |139500 |-0.2289% | |consumer-typeset|295684 |290196 |-1.8560% | |pairlocalalign |72236 |72092 |-0.1993% | |tramp3d-v4 |189572 |189292 |-0.1477% | This is part of an enhanced version of machine outliner -- see [RFC](https://discourse.llvm.org/t/rfc-enhanced-machine-outliner-part-1-fulllto-part-2-thinlto-nolto-to-come/78732).
179 lines
6.6 KiB
YAML
179 lines
6.6 KiB
YAML
# RUN: llc -mtriple=armv7-- -run-pass=prologepilog -run-pass=machine-outliner \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @CheckAddrMode_i12() { ret void }
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define void @CheckAddrMode3() { ret void }
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define void @CheckAddrMode5() { ret void }
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define void @CheckAddrMode5FP16() { ret void }
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define void @foo() { ret void }
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...
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---
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name: CheckAddrMode_i12
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0
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; CHECK-LABEL: name: CheckAddrMode_i12
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; CHECK: $r1 = MOVr killed $r0, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp
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; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I12:[0-9]+]]
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; CHECK-NEXT: $r6 = LDRi12 $sp, 4088, 14 /* CC::al */, $noreg
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$r1 = MOVr killed $r0, 14, $noreg, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$r1 = LDRi12 $sp, 0, 14, $noreg
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$r2 = LDRi12 $sp, 8, 14, $noreg
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$r5 = LDRi12 $sp, 4086, 14, $noreg
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$r6 = LDRi12 $sp, 4088, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$r1 = LDRi12 $sp, 0, 14, $noreg
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$r2 = LDRi12 $sp, 8, 14, $noreg
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$r5 = LDRi12 $sp, 4086, 14, $noreg
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$r6 = LDRi12 $sp, 4088, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$r1 = LDRi12 $sp, 0, 14, $noreg
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$r2 = LDRi12 $sp, 8, 14, $noreg
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$r5 = LDRi12 $sp, 4086, 14, $noreg
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$r6 = LDRi12 $sp, 4088, 14, $noreg
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BX_RET 14, $noreg
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...
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---
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name: CheckAddrMode3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r1
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; CHECK-LABEL: name: CheckAddrMode3
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; CHECK: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp
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; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I3:[0-9]+]]
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; CHECK-NEXT: $r6 = LDRSH $sp, $noreg, 248, 14 /* CC::al */, $noreg
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$r0 = MOVr killed $r1, 14, $noreg, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$r1 = LDRSH $sp, $noreg, 0, 14, $noreg
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$r2 = LDRSH $sp, $noreg, 8, 14, $noreg
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$r5 = LDRSH $sp, $noreg, 247, 14, $noreg
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$r6 = LDRSH $sp, $noreg, 248, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$r1 = LDRSH $sp, $noreg, 0, 14, $noreg
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$r2 = LDRSH $sp, $noreg, 8, 14, $noreg
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$r5 = LDRSH $sp, $noreg, 247, 14, $noreg
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$r6 = LDRSH $sp, $noreg, 248, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$r1 = LDRSH $sp, $noreg, 0, 14, $noreg
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$r2 = LDRSH $sp, $noreg, 8, 14, $noreg
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$r5 = LDRSH $sp, $noreg, 247, 14, $noreg
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$r6 = LDRSH $sp, $noreg, 248, 14, $noreg
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BX_RET 14, $noreg
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...
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---
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name: CheckAddrMode5
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r2
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; CHECK-LABEL: name: CheckAddrMode5
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; CHECK: $r0 = MOVr killed $r2, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp
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; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I5:[0-9]+]]
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; CHECK-NEXT: $d5 = VLDRD $sp, 254, 14 /* CC::al */, $noreg
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$r0 = MOVr killed $r2, 14, $noreg, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$d0 = VLDRD $sp, 0, 14, $noreg
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$d1 = VLDRD $sp, 8, 14, $noreg
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$d4 = VLDRD $sp, 253, 14, $noreg
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$d5 = VLDRD $sp, 254, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$d0 = VLDRD $sp, 0, 14, $noreg
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$d1 = VLDRD $sp, 8, 14, $noreg
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$d4 = VLDRD $sp, 253, 14, $noreg
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$d5 = VLDRD $sp, 254, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$d0 = VLDRD $sp, 0, 14, $noreg
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$d1 = VLDRD $sp, 8, 14, $noreg
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$d4 = VLDRD $sp, 253, 14, $noreg
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$d5 = VLDRD $sp, 254, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$d0 = VLDRD $sp, 0, 14, $noreg
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$d1 = VLDRD $sp, 8, 14, $noreg
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$d4 = VLDRD $sp, 253, 14, $noreg
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$d5 = VLDRD $sp, 254, 14, $noreg
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BX_RET 14, $noreg
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...
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---
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name: CheckAddrMode5FP16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r3
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; CHECK-LABEL: name: CheckAddrMode5FP16
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; CHECK: $r0 = MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp
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; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I5FP16:[0-9]+]]
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; CHECK-NEXT: $s6 = VLDRH $sp, 252, 14, $noreg
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$r0 = MOVr killed $r3, 14, $noreg, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$s1 = VLDRH $sp, 0, 14, $noreg
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$s2 = VLDRH $sp, 8, 14, $noreg
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$s5 = VLDRH $sp, 240, 14, $noreg
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$s6 = VLDRH $sp, 252, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$s1 = VLDRH $sp, 0, 14, $noreg
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$s2 = VLDRH $sp, 8, 14, $noreg
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$s5 = VLDRH $sp, 240, 14, $noreg
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$s6 = VLDRH $sp, 252, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$s1 = VLDRH $sp, 0, 14, $noreg
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$s2 = VLDRH $sp, 8, 14, $noreg
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$s5 = VLDRH $sp, 240, 14, $noreg
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$s6 = VLDRH $sp, 252, 14, $noreg
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BL @foo, implicit-def dead $lr, implicit $sp
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$s1 = VLDRH $sp, 0, 14, $noreg
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$s2 = VLDRH $sp, 8, 14, $noreg
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$s5 = VLDRH $sp, 240, 14, $noreg
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$s6 = VLDRH $sp, 252, 14, $noreg
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BX_RET 14, $noreg
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...
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $lr
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BX_RET 14, $noreg
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;CHECK: name: OUTLINED_FUNCTION_[[I5]]
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;CHECK: liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
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;CHECK: $d0 = VLDRD $sp, 0, 14 /* CC::al */, $noreg
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;CHECK-NEXT: $d1 = VLDRD $sp, 8, 14 /* CC::al */, $noreg
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;CHECK-NEXT: $d4 = VLDRD $sp, 253, 14 /* CC::al */, $noreg
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;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
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;CHECK: name: OUTLINED_FUNCTION_[[I5FP16]]
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;CHECK: liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8
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;CHECK: $s1 = VLDRH $sp, 0, 14, $noreg
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;CHECK-NEXT: $s2 = VLDRH $sp, 8, 14, $noreg
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;CHECK-NEXT: $s5 = VLDRH $sp, 240, 14, $noreg
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;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
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;CHECK: name: OUTLINED_FUNCTION_[[I12]]
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;CHECK: liveins: $r10, $r9, $r8, $r7, $d8, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9
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;CHECK: $r1 = LDRi12 $sp, 0, 14 /* CC::al */, $noreg
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;CHECK-NEXT: $r2 = LDRi12 $sp, 8, 14 /* CC::al */, $noreg
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;CHECK-NEXT: $r5 = LDRi12 $sp, 4086, 14 /* CC::al */, $noreg
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;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
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;CHECK: name: OUTLINED_FUNCTION_[[I3]]
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;CHECK: liveins: $r10, $r9, $r8, $r7, $d8, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9
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;CHECK: $r1 = LDRSH $sp, $noreg, 0, 14 /* CC::al */, $noreg
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;CHECK-NEXT: $r2 = LDRSH $sp, $noreg, 8, 14 /* CC::al */, $noreg
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;CHECK-NEXT: $r5 = LDRSH $sp, $noreg, 247, 14 /* CC::al */, $noreg
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;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
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