7852ebc088
Before llvm20, (void)__sync_fetch_and_add(...) always generates locked xadd insns. In linux kernel upstream discussion [1], it is found that for arm64 architecture, the original semantics of (void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is preferred in order for jit to emit proper native barrier insns. In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will generate the following insns: - for cpu v1/v2: locked xadd insns to keep backward compatibility - for cpu v3/v4: __atomic_fetch_add() insns To ensure proper barrier semantics for (void)__sync_fetch_and_add(...), cpu v3/v4 is recommended. This patch enables cpu=v3 as the default cpu version. For users wanting to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc command line. [1] https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f [2] https://github.com/llvm/llvm-project/pull/101428 [3] https://github.com/llvm/llvm-project/pull/106494
29 lines
601 B
LLVM
29 lines
601 B
LLVM
; RUN: llc < %s -march=bpfel -mcpu=v1 | FileCheck %s
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define i32 @test0(i32 %X) {
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%tmp.1 = add i32 %X, 1
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ret i32 %tmp.1
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; CHECK-LABEL: test0:
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; CHECK: r0 += 1
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}
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; CHECK-LABEL: store_imm:
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; CHECK: *(u32 *)(r1 + 0) = r{{[03]}}
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; CHECK: *(u32 *)(r2 + 4) = r{{[03]}}
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define i32 @store_imm(ptr %a, ptr %b) {
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entry:
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store i32 0, ptr %a, align 4
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%0 = getelementptr inbounds i32, ptr %b, i32 1
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store i32 0, ptr %0, align 4
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ret i32 0
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}
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@G = external global i8
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define zeroext i8 @loadG() {
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%tmp = load i8, ptr @G
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ret i8 %tmp
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; CHECK-LABEL: loadG:
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; CHECK: r1 =
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; CHECK: r0 = *(u8 *)(r1 + 0)
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}
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