Before llvm20, (void)__sync_fetch_and_add(...) always generates locked xadd insns. In linux kernel upstream discussion [1], it is found that for arm64 architecture, the original semantics of (void)__sync_fetch_and_add(...), i.e., __atomic_fetch_add(...), is preferred in order for jit to emit proper native barrier insns. In llvm commits [2] and [3], (void)__sync_fetch_and_add(...) will generate the following insns: - for cpu v1/v2: locked xadd insns to keep backward compatibility - for cpu v3/v4: __atomic_fetch_add() insns To ensure proper barrier semantics for (void)__sync_fetch_and_add(...), cpu v3/v4 is recommended. This patch enables cpu=v3 as the default cpu version. For users wanting to use cpu v1, -mcpu=v1 needs to be explicitly added to clang/llc command line. [1] https://lore.kernel.org/bpf/ZqqiQQWRnz7H93Hc@google.com/T/#mb68d67bc8f39e35a0c3db52468b9de59b79f021f [2] https://github.com/llvm/llvm-project/pull/101428 [3] https://github.com/llvm/llvm-project/pull/106494
49 lines
876 B
LLVM
49 lines
876 B
LLVM
; RUN: llc < %s -march=bpfel -mcpu=v1 | FileCheck %s
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define void @test() #0 {
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entry:
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; CHECK: test:
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; CHECK: call f_i16
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; CHECK: *(u16 *)(r1 + 0) = r0
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%0 = call i16 @f_i16()
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store volatile i16 %0, ptr @g_i16
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; CHECK: call f_i32
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; CHECK: *(u32 *)(r1 + 0) = r0
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%1 = call i32 @f_i32()
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store volatile i32 %1, ptr @g_i32
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; CHECK: call f_i64
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; CHECK: *(u64 *)(r1 + 0) = r0
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%2 = call i64 @f_i64()
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store volatile i64 %2, ptr @g_i64
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ret void
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}
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@g_i16 = common global i16 0, align 2
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@g_i32 = common global i32 0, align 2
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@g_i64 = common global i64 0, align 2
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define i16 @f_i16() #0 {
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; CHECK: f_i16:
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; CHECK: r0 = 1
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; CHECK: exit
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ret i16 1
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}
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define i32 @f_i32() #0 {
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; CHECK: f_i32:
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; CHECK: r0 = 16909060
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; CHECK: exit
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ret i32 16909060
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}
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define i64 @f_i64() #0 {
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; CHECK: f_i64:
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; CHECK: r0 = 72623859790382856 ll
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; CHECK: exit
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ret i64 72623859790382856
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}
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