9d4f7f44b6
Because most of tests assume target-abi=`lp64d`, adding the
corresponding feature is reasonable.
rg -l loongarch -g '!*.s' | xargs sed -i '/mtriple=loongarch/ {/-mattr=/!{/target-abi/! s/mtriple=loongarch.. /&-mattr=+d /}}'
99 lines
2.5 KiB
LLVM
99 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s
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define i64 @lshr40_and255(i64 %a) {
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; CHECK-LABEL: lshr40_and255:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.d $a0, $a0, 47, 40
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; CHECK-NEXT: ret
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%shr = lshr i64 %a, 40
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%and = and i64 %shr, 255
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ret i64 %and
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}
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define i64 @ashr50_and511(i64 %a) {
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; CHECK-LABEL: ashr50_and511:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.d $a0, $a0, 58, 50
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; CHECK-NEXT: ret
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%shr = ashr i64 %a, 50
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%and = and i64 %shr, 511
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ret i64 %and
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}
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define i64 @zext_i32_to_i64(i32 %a) {
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; CHECK-LABEL: zext_i32_to_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.d $a0, $a0, 31, 0
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; CHECK-NEXT: ret
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%res = zext i32 %a to i64
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ret i64 %res
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}
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define i64 @and8191(i64 %a) {
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; CHECK-LABEL: and8191:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.d $a0, $a0, 12, 0
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; CHECK-NEXT: ret
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%and = and i64 %a, 8191
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ret i64 %and
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}
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;; Check that andi but not bstrpick.d is generated.
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define i64 @and4095(i64 %a) {
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; CHECK-LABEL: and4095:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi $a0, $a0, 4095
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; CHECK-NEXT: ret
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%and = and i64 %a, 4095
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ret i64 %and
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}
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;; (srl (and a, 0xff0), 4) => (BSTRPICK a, 11, 4)
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define i64 @and0xff0_lshr4(i64 %a) {
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; CHECK-LABEL: and0xff0_lshr4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.d $a0, $a0, 11, 4
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; CHECK-NEXT: ret
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%and = and i64 %a, 4080
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%shr = lshr i64 %and, 4
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ret i64 %shr
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}
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;; (sra (and a, 0xff0), 5) can also be combined to (BSTRPICK a, 11, 5).
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;; This is because (sra (and a, 0xff0)) would be combined to (srl (and a, 0xff0), 5)
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;; firstly by DAGCombiner::SimplifyDemandedBits.
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define i64 @and4080_ashr5(i64 %a) {
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; CHECK-LABEL: and4080_ashr5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bstrpick.d $a0, $a0, 11, 5
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; CHECK-NEXT: ret
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%and = and i64 %a, 4080
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%shr = ashr i64 %and, 5
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ret i64 %shr
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}
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;; Negative test: the second operand of AND is not a shifted mask
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define i64 @and0xf30_lshr4(i64 %a) {
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; CHECK-LABEL: and0xf30_lshr4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi $a0, $a0, 3888
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; CHECK-NEXT: srli.d $a0, $a0, 4
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; CHECK-NEXT: ret
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%and = and i64 %a, 3888
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%shr = lshr i64 %and, 4
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ret i64 %shr
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}
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;; Negative test: Shamt < MaskIdx
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define i64 @and0xff0_lshr3(i64 %a) {
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; CHECK-LABEL: and0xff0_lshr3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi $a0, $a0, 4080
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; CHECK-NEXT: srli.d $a0, $a0, 3
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; CHECK-NEXT: ret
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%and = and i64 %a, 4080
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%shr = lshr i64 %and, 3
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ret i64 %shr
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}
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