3e0a76b1fd
Minor improvement on cc39c3b17f.
Use an aligned stack slot to store the shifted value.
Use the native register width as shifting unit, so the load of the
shift result is aligned.
If the shift amount is a multiple of the native register width, there is
no need to do a follow-up shift after the load. I added new tests for
these cases.
Co-authored-by: Gergely Futo <gergely.futo@hightec-rt.com>
128 lines
3.8 KiB
LLVM
128 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE64
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; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE32
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; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE64
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; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE32
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; To verify this doesn't crash due to array out of bound.
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define void @pr59074(ptr %0) {
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; LE64-LABEL: pr59074:
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; LE64: # %bb.0: # %entry
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; LE64-NEXT: lwz 6, 0(3)
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; LE64-NEXT: li 7, 12
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; LE64-NEXT: ld 4, 16(3)
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; LE64-NEXT: ld 5, 24(3)
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; LE64-NEXT: addi 6, 6, -12
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; LE64-NEXT: std 4, 16(3)
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; LE64-NEXT: std 5, 24(3)
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; LE64-NEXT: srd 6, 7, 6
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; LE64-NEXT: li 7, 0
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; LE64-NEXT: std 7, 8(3)
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; LE64-NEXT: std 6, 0(3)
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; LE64-NEXT: blr
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;
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; LE32-LABEL: pr59074:
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; LE32: # %bb.0: # %entry
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; LE32-NEXT: stwu 1, -80(1)
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; LE32-NEXT: .cfi_def_cfa_offset 80
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; LE32-NEXT: lwz 4, 0(3)
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; LE32-NEXT: xxlxor 0, 0, 0
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; LE32-NEXT: li 5, 4
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; LE32-NEXT: addi 6, 1, 16
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; LE32-NEXT: li 7, 0
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; LE32-NEXT: li 8, 12
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; LE32-NEXT: xxswapd 0, 0
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; LE32-NEXT: rlwimi 5, 6, 0, 30, 28
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; LE32-NEXT: addi 4, 4, -12
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; LE32-NEXT: rlwinm 9, 4, 29, 28, 29
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; LE32-NEXT: stxvd2x 0, 0, 5
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; LE32-NEXT: stw 7, 44(1)
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; LE32-NEXT: stw 7, 40(1)
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; LE32-NEXT: stw 7, 36(1)
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; LE32-NEXT: stw 8, 16(1)
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; LE32-NEXT: clrlwi 4, 4, 27
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; LE32-NEXT: lwzux 5, 9, 6
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; LE32-NEXT: lwz 6, 8(9)
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; LE32-NEXT: lwz 7, 4(9)
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; LE32-NEXT: lwz 8, 12(9)
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; LE32-NEXT: xori 9, 4, 31
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; LE32-NEXT: subfic 11, 4, 32
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; LE32-NEXT: srw 5, 5, 4
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; LE32-NEXT: slwi 10, 6, 1
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; LE32-NEXT: srw 6, 6, 4
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; LE32-NEXT: slw 9, 10, 9
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; LE32-NEXT: srw 10, 7, 4
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; LE32-NEXT: slw 7, 7, 11
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; LE32-NEXT: slw 11, 8, 11
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; LE32-NEXT: srw 4, 8, 4
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; LE32-NEXT: or 5, 7, 5
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; LE32-NEXT: or 6, 11, 6
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; LE32-NEXT: or 7, 10, 9
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; LE32-NEXT: stw 4, 12(3)
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; LE32-NEXT: stw 6, 8(3)
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; LE32-NEXT: stw 5, 0(3)
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; LE32-NEXT: stw 7, 4(3)
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; LE32-NEXT: addi 1, 1, 80
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; LE32-NEXT: blr
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;
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; BE64-LABEL: pr59074:
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; BE64: # %bb.0: # %entry
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; BE64-NEXT: lwz 6, 12(3)
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; BE64-NEXT: li 7, 12
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; BE64-NEXT: ld 4, 24(3)
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; BE64-NEXT: ld 5, 16(3)
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; BE64-NEXT: addi 6, 6, -12
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; BE64-NEXT: std 4, 24(3)
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; BE64-NEXT: std 5, 16(3)
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; BE64-NEXT: srd 6, 7, 6
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; BE64-NEXT: li 7, 0
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; BE64-NEXT: std 7, 0(3)
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; BE64-NEXT: std 6, 8(3)
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; BE64-NEXT: blr
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;
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; BE32-LABEL: pr59074:
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; BE32: # %bb.0: # %entry
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; BE32-NEXT: lwz 4, 12(3)
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; BE32-NEXT: xxlxor 0, 0, 0
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; BE32-NEXT: addi 5, 1, -64
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; BE32-NEXT: li 6, 12
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; BE32-NEXT: li 7, 0
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; BE32-NEXT: addi 8, 1, -48
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; BE32-NEXT: stxvw4x 0, 0, 5
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; BE32-NEXT: stw 6, -36(1)
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; BE32-NEXT: addi 4, 4, -12
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; BE32-NEXT: stw 7, -40(1)
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; BE32-NEXT: stw 7, -44(1)
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; BE32-NEXT: stw 7, -48(1)
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; BE32-NEXT: rlwinm 9, 4, 29, 28, 29
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; BE32-NEXT: clrlwi 4, 4, 27
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; BE32-NEXT: sub 5, 8, 9
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; BE32-NEXT: lwz 6, 4(5)
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; BE32-NEXT: lwz 7, 0(5)
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; BE32-NEXT: lwz 8, 12(5)
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; BE32-NEXT: lwz 5, 8(5)
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; BE32-NEXT: subfic 10, 4, 32
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; BE32-NEXT: srw 9, 6, 4
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; BE32-NEXT: slw 11, 7, 10
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; BE32-NEXT: srw 8, 8, 4
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; BE32-NEXT: slw 6, 6, 10
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; BE32-NEXT: slw 10, 5, 10
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; BE32-NEXT: srw 5, 5, 4
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; BE32-NEXT: srw 4, 7, 4
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; BE32-NEXT: or 7, 11, 9
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; BE32-NEXT: or 8, 10, 8
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; BE32-NEXT: or 5, 6, 5
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; BE32-NEXT: stw 4, 0(3)
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; BE32-NEXT: stw 5, 8(3)
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; BE32-NEXT: stw 8, 12(3)
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; BE32-NEXT: stw 7, 4(3)
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; BE32-NEXT: blr
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entry:
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%v1 = load <2 x i128>, <2 x i128>* %0
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%v2 = insertelement <2 x i128> %v1, i128 12, i32 0
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%v3 = sub <2 x i128> %v1, %v2
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%v4 = lshr <2 x i128> %v2, %v3
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store <2 x i128> %v4, <2 x i128>* %0
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ret void
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}
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