Files
clang-p2996/llvm/test/CodeGen/PowerPC/uaddo-32.ll
Zaara Syeda c5ca1b8626 [PPC] Add custom lowering for uaddo (#110137)
Improve the codegen for uaddo node for i64 in 64-bit mode and i32 in
32-bit mode by custom lowering.
2024-10-21 11:13:16 -04:00

39 lines
1.3 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
define noundef i32 @add(i32 noundef %a, i32 noundef %b, ptr nocapture noundef writeonly %ovf) {
; CHECK-LABEL: add:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 6, 0
; CHECK-NEXT: addc 3, 3, 4
; CHECK-NEXT: addze 4, 6
; CHECK-NEXT: stw 4, 0(5)
; CHECK-NEXT: blr
entry:
%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%1 = extractvalue { i32, i1 } %0, 1
%2 = extractvalue { i32, i1 } %0, 0
%3 = zext i1 %1 to i32
store i32 %3, ptr %ovf, align 8
ret i32 %2
}
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32)
define noundef zeroext i1 @add_overflow(i32 noundef %a, i32 noundef %b, ptr nocapture noundef writeonly %ovf) {
; CHECK-LABEL: add_overflow:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 6, 0
; CHECK-NEXT: addc 4, 3, 4
; CHECK-NEXT: addze 3, 6
; CHECK-NEXT: stw 4, 0(5)
; CHECK-NEXT: blr
entry:
%0 = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
%1 = extractvalue { i32, i1 } %0, 1
%2 = extractvalue { i32, i1 } %0, 0
store i32 %2, ptr %ovf, align 8
ret i1 %1
}