c5ca1b8626
Improve the codegen for uaddo node for i64 in 64-bit mode and i32 in 32-bit mode by custom lowering.
63 lines
2.1 KiB
LLVM
63 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
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define noundef i64 @add(i64 noundef %a, i64 noundef %b, ptr nocapture noundef writeonly %ovf) {
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; CHECK-LABEL: add:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 6, 0
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; CHECK-NEXT: addc 3, 3, 4
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; CHECK-NEXT: addze 4, 6
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; CHECK-NEXT: std 4, 0(5)
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; CHECK-NEXT: blr
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entry:
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%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%1 = extractvalue { i64, i1 } %0, 1
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%2 = extractvalue { i64, i1 } %0, 0
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%3 = zext i1 %1 to i64
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store i64 %3, ptr %ovf, align 8
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ret i64 %2
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}
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declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64)
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define noundef zeroext i1 @add_overflow(i64 noundef %a, i64 noundef %b, ptr nocapture noundef writeonly %ovf) {
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; CHECK-LABEL: add_overflow:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 6, 0
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; CHECK-NEXT: addc 4, 3, 4
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; CHECK-NEXT: addze 3, 6
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; CHECK-NEXT: std 4, 0(5)
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; CHECK-NEXT: blr
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entry:
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%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%1 = extractvalue { i64, i1 } %0, 1
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%2 = extractvalue { i64, i1 } %0, 0
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store i64 %2, ptr %ovf, align 8
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ret i1 %1
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}
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define noundef i64 @addWithCarryIn (i64 noundef %a, i64 noundef %b, i64 noundef %c, ptr nocapture noundef writeonly %ovf) {
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; CHECK-LABEL: addWithCarryIn:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 7, 0
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; CHECK-NEXT: addc 3, 3, 4
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; CHECK-NEXT: addze 4, 7
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; CHECK-NEXT: addc 3, 3, 5
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; CHECK-NEXT: addze 5, 7
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; CHECK-NEXT: or 4, 4, 5
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; CHECK-NEXT: std 4, 0(6)
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; CHECK-NEXT: blr
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entry:
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%0 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%1 = extractvalue { i64, i1 } %0, 1
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%2 = extractvalue { i64, i1 } %0, 0
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%3 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %2, i64 %c)
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%4 = extractvalue { i64, i1 } %3, 1
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%5 = extractvalue { i64, i1 } %3, 0
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%6 = or i1 %1, %4
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%7 = zext i1 %6 to i64
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store i64 %7, ptr %ovf, align 8
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ret i64 %5
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}
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