67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
50 lines
1.5 KiB
LLVM
50 lines
1.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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define half @getConstantFP16() {
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ret half 0x3ff1340000000000 ; 0x3c4d represented as double.
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}
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define float @getConstantFP32() {
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ret float 0x3fd27c8be0000000 ; 0x3e93e45f represented as double
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}
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define double @getConstantFP64() {
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ret double 0x4f2de42b8c68f3f1
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}
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;; Capabilities
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; CHECK-DAG: OpCapability Float16
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; CHECK-DAG: OpCapability Float64
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; CHECK-NOT: DAG-FENCE
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;; Names:
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; CHECK-DAG: OpName %[[#GET_FP16:]] "getConstantFP16"
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; CHECK-DAG: OpName %[[#GET_FP32:]] "getConstantFP32"
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; CHECK-DAG: OpName %[[#GET_FP64:]] "getConstantFP64"
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; CHECK-NOT: DAG-FENCE
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;; Types and Constants:
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;; NOTE: These tests don't actually check the values of the constants because
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;; their representation isn't defined for textual output.
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;; TODO: Test constant representation using binary output.
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; CHECK-DAG: %[[#FP16:]] = OpTypeFloat 16
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; CHECK-DAG: %[[#FP32:]] = OpTypeFloat 32
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; CHECK-DAG: %[[#FP64:]] = OpTypeFloat 64
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; CHECK-DAG: %[[#CST_FP16:]] = OpConstant %[[#FP16]]
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; CHECK-DAG: %[[#CST_FP32:]] = OpConstant %[[#FP32]]
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; CHECK-DAG: %[[#CST_FP64:]] = OpConstant %[[#FP64]]
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; CHECK: %[[#GET_FP16]] = OpFunction %[[#FP16]]
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; CHECK: OpReturnValue %[[#CST_FP16]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#GET_FP32]] = OpFunction %[[#FP32]]
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; CHECK: OpReturnValue %[[#CST_FP32]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#GET_FP64]] = OpFunction %[[#FP64]]
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; CHECK: OpReturnValue %[[#CST_FP64]]
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; CHECK: OpFunctionEnd
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