67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
107 lines
3.4 KiB
LLVM
107 lines
3.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; CHECK-DAG: OpName [[VECTOR_SHL:%.+]] "vector_shl"
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; CHECK-DAG: OpName [[VECTOR_LSHR:%.+]] "vector_lshr"
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; CHECK-DAG: OpName [[VECTOR_ASHR:%.+]] "vector_ashr"
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; CHECK-DAG: OpName [[VECTOR_AND:%.+]] "vector_and"
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; CHECK-DAG: OpName [[VECTOR_OR:%.+]] "vector_or"
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; CHECK-DAG: OpName [[VECTOR_XOR:%.+]] "vector_xor"
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; CHECK-NOT: DAG-FENCE
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; CHECK-DAG: [[I16:%.+]] = OpTypeInt 16
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; CHECK-DAG: [[VECTOR:%.+]] = OpTypeVector [[I16]]
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; CHECK-DAG: [[VECTOR_FN:%.+]] = OpTypeFunction [[VECTOR]] [[VECTOR]] [[VECTOR]]
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; CHECK-NOT: DAG-FENCE
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;; Test shl on vector:
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define <2 x i16> @vector_shl(<2 x i16> %a, <2 x i16> %b) {
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%c = shl <2 x i16> %a, %b
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ret <2 x i16> %c
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}
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; CHECK: [[VECTOR_SHL]] = OpFunction [[VECTOR]] None [[VECTOR_FN]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK: OpLabel
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; CHECK: [[C:%.+]] = OpShiftLeftLogical [[VECTOR]] [[A]] [[B]]
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; CHECK: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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;; Test lshr on vector:
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define <2 x i16> @vector_lshr(<2 x i16> %a, <2 x i16> %b) {
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%c = lshr <2 x i16> %a, %b
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ret <2 x i16> %c
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}
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; CHECK: [[VECTOR_LSHR]] = OpFunction [[VECTOR]] None [[VECTOR_FN]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK: OpLabel
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; CHECK: [[C:%.+]] = OpShiftRightLogical [[VECTOR]] [[A]] [[B]]
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; CHECK: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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;; Test ashr on vector:
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define <2 x i16> @vector_ashr(<2 x i16> %a, <2 x i16> %b) {
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%c = ashr <2 x i16> %a, %b
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ret <2 x i16> %c
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}
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; CHECK: [[VECTOR_ASHR]] = OpFunction [[VECTOR]] None [[VECTOR_FN]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK: OpLabel
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; CHECK: [[C:%.+]] = OpShiftRightArithmetic [[VECTOR]] [[A]] [[B]]
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; CHECK: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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;; Test and on vector:
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define <2 x i16> @vector_and(<2 x i16> %a, <2 x i16> %b) {
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%c = and <2 x i16> %a, %b
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ret <2 x i16> %c
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}
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; CHECK: [[VECTOR_AND]] = OpFunction [[VECTOR]] None [[VECTOR_FN]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK: OpLabel
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; CHECK: [[C:%.+]] = OpBitwiseAnd [[VECTOR]] [[A]] [[B]]
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; CHECK: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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;; Test or on vector:
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define <2 x i16> @vector_or(<2 x i16> %a, <2 x i16> %b) {
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%c = or <2 x i16> %a, %b
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ret <2 x i16> %c
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}
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; CHECK: [[VECTOR_OR]] = OpFunction [[VECTOR]] None [[VECTOR_FN]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK: OpLabel
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; CHECK: [[C:%.+]] = OpBitwiseOr [[VECTOR]] [[A]] [[B]]
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; CHECK: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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;; Test xor on vector:
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define <2 x i16> @vector_xor(<2 x i16> %a, <2 x i16> %b) {
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%c = xor <2 x i16> %a, %b
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ret <2 x i16> %c
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}
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; CHECK: [[VECTOR_XOR]] = OpFunction [[VECTOR]] None [[VECTOR_FN]]
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; CHECK-NEXT: [[A:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK-NEXT: [[B:%.+]] = OpFunctionParameter [[VECTOR]]
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; CHECK: OpLabel
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; CHECK: [[C:%.+]] = OpBitwiseXor [[VECTOR]] [[A]] [[B]]
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; CHECK: OpReturnValue [[C]]
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; CHECK-NEXT: OpFunctionEnd
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