1ed65febd9
This commit adds an initial SPIR-V structurizer. It leverages the previously merged passes, and the convergence region analysis to determine the correct merge and continue blocks for SPIR-V. The first part does a branch cleanup (simplifying switches, and legalizing them), then merge instructions are added to cycles, convergent and later divergent blocks. Then comes the important part: splitting critical edges, and making sure the divergent construct boundaries don't cross. - we split blocks with multiple headers into 2 blocks. - we split blocks that are a merge blocks for 2 or more constructs: SPIR-V spec disallow a merge block to be shared by 2 loop/switch/condition construct. - we split merge & continue blocks: SPIR-V spec disallow a basic block to be both a continue block, and a merge block. - we remove superfluous headers: when a header doesn't bring more info than the parent on the divergence state, it must be removed. This PR leverages the merged SPIR-V simulator for testing, as long as spirv-val. For now, most DXC structurization tests are passing. The unsupported ones are either caused by unsupported features like switches on boolean types, or switches in region exits, because the MergeExit pass doesn't support those yet (there is a FIXME). This PR is quite large, and the addition not trivial, so I tried to keep it simple. E.G: as soon as the CFG changes, I recompute the dominator trees and other structures instead of updating them. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
508 lines
17 KiB
LLVM
508 lines
17 KiB
LLVM
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=308
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;
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; int foo() { return 200; }
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;
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; int process() {
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; int a = 0;
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; int b = 0;
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; int c = 0;
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; const int r = 20;
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; const int s = 40;
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; const int t = 3*r+2*s;
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;
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;
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; ////////////////////////////////////////
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; // DefaultStmt is the first statement //
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; ////////////////////////////////////////
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; switch(a) {
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; default:
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; b += 0;
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; case 1:
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; b += 1;
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; break;
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; case 2:
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; b += 2;
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; }
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;
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;
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; //////////////////////////////////////////////
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; // DefaultStmt in the middle of other cases //
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; //////////////////////////////////////////////
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; switch(a) {
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; case 10:
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; b += 1;
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; default:
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; b += 0;
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; case 20:
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; b += 2;
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; break;
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; }
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;
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; ///////////////////////////////////////////////
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; // Various CaseStmt and BreakStmt topologies //
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; // DefaultStmt is the last statement //
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; ///////////////////////////////////////////////
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; switch(int d = 5) {
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; case 1:
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; b += 1;
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; c += foo();
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; case 2:
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; b += 2;
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; break;
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; case 3:
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; {
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; b += 3;
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; break;
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; }
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; case t:
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; b += t;
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; case 4:
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; case 5:
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; b += 5;
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; break;
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; case 6: {
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; case 7:
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; break;}
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; default:
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; break;
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; }
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;
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;
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; //////////////////////////
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; // No Default statement //
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; //////////////////////////
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; switch(a) {
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; case 100:
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; b += 100;
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; break;
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; }
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;
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;
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; /////////////////////////////////////////////////////////
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; // No cases. Only a default //
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; // This means the default body will always be executed //
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; /////////////////////////////////////////////////////////
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; switch(a) {
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; default:
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; b += 100;
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; c += 200;
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; break;
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; }
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;
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;
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; ////////////////////////////////////////////////////////////
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; // Nested Switch with branching //
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; // The two inner switch statements should be executed for //
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; // both cases of the outer switch (case 300 and case 400) //
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; ////////////////////////////////////////////////////////////
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; switch(a) {
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; case 300:
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; b += 300;
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; case 400:
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; switch(c) {
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; case 500:
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; b += 500;
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; break;
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; case 600:
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; switch(b) {
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; default:
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; a += 600;
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; b += 600;
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; }
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; }
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; }
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;
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; return a + b + c;
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; }
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;
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; [numthreads(1, 1, 1)]
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; void main() {
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; process();
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; }
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; CHECK: %[[#func_22:]] = OpFunction %[[#uint:]] DontInline %[[#]]
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; CHECK: %[[#bb94:]] = OpLabel
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; CHECK: OpReturnValue %[[#]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_23:]] = OpFunction %[[#uint:]] DontInline %[[#]]
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; CHECK: %[[#bb95:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb96:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb97:]] %[[#bb98:]]
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; CHECK: %[[#bb97:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb99:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb100:]] 1 %[[#bb99:]] 2 %[[#bb101:]]
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; CHECK: %[[#bb98:]] = OpLabel
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; CHECK: %[[#bb100:]] = OpLabel
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; CHECK: OpBranch %[[#bb99:]]
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; CHECK: %[[#bb101:]] = OpLabel
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; CHECK: OpBranch %[[#bb99:]]
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; CHECK: %[[#bb99:]] = OpLabel
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; CHECK: OpBranchConditional %[[#]] %[[#bb102:]] %[[#bb96:]]
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; CHECK: %[[#bb102:]] = OpLabel
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; CHECK: OpBranch %[[#bb96:]]
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; CHECK: %[[#bb96:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb103:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb104:]] %[[#bb105:]]
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; CHECK: %[[#bb104:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb106:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb106:]] 10 %[[#bb107:]] 20 %[[#bb108:]]
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; CHECK: %[[#bb105:]] = OpLabel
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; CHECK: %[[#bb107:]] = OpLabel
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; CHECK: OpBranch %[[#bb106:]]
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; CHECK: %[[#bb108:]] = OpLabel
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; CHECK: OpBranch %[[#bb106:]]
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; CHECK: %[[#bb106:]] = OpLabel
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; CHECK: OpBranchConditional %[[#]] %[[#bb109:]] %[[#bb103:]]
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; CHECK: %[[#bb109:]] = OpLabel
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; CHECK: OpBranch %[[#bb103:]]
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; CHECK: %[[#bb103:]] = OpLabel
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; CHECK: OpBranch %[[#bb110:]]
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; CHECK: %[[#bb110:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb111:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb112:]] %[[#bb113:]]
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; CHECK: %[[#bb112:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb114:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb115:]] %[[#bb116:]]
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; CHECK: %[[#bb113:]] = OpLabel
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; CHECK: %[[#bb115:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb117:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb118:]] %[[#bb119:]]
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; CHECK: %[[#bb116:]] = OpLabel
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; CHECK: %[[#bb118:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb120:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb121:]] 1 %[[#bb122:]] 2 %[[#bb120:]] 3 %[[#bb123:]] 140 %[[#bb124:]] 4 %[[#bb125:]] 5 %[[#bb126:]] 6 %[[#bb127:]] 7 %[[#bb128:]]
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; CHECK: %[[#bb119:]] = OpLabel
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; CHECK: %[[#bb121:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb122:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb123:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb124:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb125:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb126:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb127:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb128:]] = OpLabel
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; CHECK: OpBranch %[[#bb120:]]
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; CHECK: %[[#bb120:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb129:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb130:]] 1 %[[#bb129:]] 2 %[[#bb131:]] 3 %[[#bb132:]]
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; CHECK: %[[#bb130:]] = OpLabel
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; CHECK: OpBranch %[[#bb129:]]
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; CHECK: %[[#bb131:]] = OpLabel
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; CHECK: OpBranch %[[#bb129:]]
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; CHECK: %[[#bb132:]] = OpLabel
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; CHECK: OpBranch %[[#bb129:]]
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; CHECK: %[[#bb129:]] = OpLabel
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; CHECK: OpBranch %[[#bb117:]]
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; CHECK: %[[#bb117:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb133:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb134:]] 1 %[[#bb133:]] 2 %[[#bb135:]]
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; CHECK: %[[#bb134:]] = OpLabel
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; CHECK: OpBranch %[[#bb133:]]
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; CHECK: %[[#bb135:]] = OpLabel
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; CHECK: OpBranch %[[#bb133:]]
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; CHECK: %[[#bb133:]] = OpLabel
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; CHECK: OpBranch %[[#bb114:]]
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; CHECK: %[[#bb114:]] = OpLabel
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; CHECK: OpBranch %[[#bb111:]]
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; CHECK: %[[#bb111:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb136:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb137:]] %[[#bb136:]]
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; CHECK: %[[#bb137:]] = OpLabel
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; CHECK: OpBranch %[[#bb136:]]
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; CHECK: %[[#bb136:]] = OpLabel
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; CHECK: OpBranch %[[#bb138:]]
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; CHECK: %[[#bb138:]] = OpLabel
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; CHECK: OpBranch %[[#bb139:]]
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; CHECK: %[[#bb139:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb140:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb141:]] %[[#bb142:]]
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; CHECK: %[[#bb141:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb143:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb143:]] 300 %[[#bb144:]] 400 %[[#bb145:]]
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; CHECK: %[[#bb142:]] = OpLabel
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; CHECK: %[[#bb144:]] = OpLabel
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; CHECK: OpBranch %[[#bb143:]]
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; CHECK: %[[#bb145:]] = OpLabel
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; CHECK: OpBranch %[[#bb143:]]
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; CHECK: %[[#bb143:]] = OpLabel
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; CHECK: OpBranchConditional %[[#]] %[[#bb140:]] %[[#bb146:]]
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; CHECK: %[[#bb146:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb147:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb147:]] 500 %[[#bb148:]] 600 %[[#bb149:]]
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; CHECK: %[[#bb148:]] = OpLabel
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; CHECK: OpBranch %[[#bb147:]]
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; CHECK: %[[#bb149:]] = OpLabel
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; CHECK: OpBranch %[[#bb150:]]
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; CHECK: %[[#bb150:]] = OpLabel
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; CHECK: OpBranch %[[#bb147:]]
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; CHECK: %[[#bb147:]] = OpLabel
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; CHECK: OpBranch %[[#bb140:]]
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; CHECK: %[[#bb140:]] = OpLabel
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; CHECK: OpReturnValue %[[#]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_90:]] = OpFunction %[[#void:]] DontInline %[[#]]
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; CHECK: %[[#bb151:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_92:]] = OpFunction %[[#void:]] None %[[#]]
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; CHECK: %[[#bb152:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define spir_func noundef i32 @_Z3foov() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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ret i32 200
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.entry() #1
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define spir_func noundef i32 @_Z7processv() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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%c = alloca i32, align 4
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%r = alloca i32, align 4
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%s = alloca i32, align 4
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%t = alloca i32, align 4
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%d = alloca i32, align 4
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store i32 0, ptr %a, align 4
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store i32 0, ptr %b, align 4
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store i32 0, ptr %c, align 4
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store i32 20, ptr %r, align 4
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store i32 40, ptr %s, align 4
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store i32 140, ptr %t, align 4
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%1 = load i32, ptr %a, align 4
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switch i32 %1, label %sw.default [
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i32 1, label %sw.bb
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i32 2, label %sw.bb2
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]
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sw.default: ; preds = %entry
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%2 = load i32, ptr %b, align 4
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%add = add nsw i32 %2, 0
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store i32 %add, ptr %b, align 4
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br label %sw.bb
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sw.bb: ; preds = %entry, %sw.default
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%3 = load i32, ptr %b, align 4
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%add1 = add nsw i32 %3, 1
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store i32 %add1, ptr %b, align 4
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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%4 = load i32, ptr %b, align 4
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%add3 = add nsw i32 %4, 2
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store i32 %add3, ptr %b, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb2, %sw.bb
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%5 = load i32, ptr %a, align 4
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switch i32 %5, label %sw.default6 [
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i32 10, label %sw.bb4
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i32 20, label %sw.bb8
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]
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sw.bb4: ; preds = %sw.epilog
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%6 = load i32, ptr %b, align 4
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%add5 = add nsw i32 %6, 1
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store i32 %add5, ptr %b, align 4
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br label %sw.default6
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sw.default6: ; preds = %sw.epilog, %sw.bb4
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%7 = load i32, ptr %b, align 4
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%add7 = add nsw i32 %7, 0
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store i32 %add7, ptr %b, align 4
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br label %sw.bb8
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sw.bb8: ; preds = %sw.epilog, %sw.default6
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%8 = load i32, ptr %b, align 4
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%add9 = add nsw i32 %8, 2
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store i32 %add9, ptr %b, align 4
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br label %sw.epilog10
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sw.epilog10: ; preds = %sw.bb8
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store i32 5, ptr %d, align 4
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%9 = load i32, ptr %d, align 4
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switch i32 %9, label %sw.default25 [
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i32 1, label %sw.bb11
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i32 2, label %sw.bb15
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i32 3, label %sw.bb17
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i32 140, label %sw.bb19
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i32 4, label %sw.bb21
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i32 5, label %sw.bb21
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i32 6, label %sw.bb23
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i32 7, label %sw.bb24
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]
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sw.bb11: ; preds = %sw.epilog10
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%10 = load i32, ptr %b, align 4
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%add12 = add nsw i32 %10, 1
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store i32 %add12, ptr %b, align 4
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%call13 = call spir_func noundef i32 @_Z3foov() #3 [ "convergencectrl"(token %0) ]
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%11 = load i32, ptr %c, align 4
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%add14 = add nsw i32 %11, %call13
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store i32 %add14, ptr %c, align 4
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br label %sw.bb15
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sw.bb15: ; preds = %sw.epilog10, %sw.bb11
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%12 = load i32, ptr %b, align 4
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%add16 = add nsw i32 %12, 2
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store i32 %add16, ptr %b, align 4
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br label %sw.epilog26
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sw.bb17: ; preds = %sw.epilog10
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%13 = load i32, ptr %b, align 4
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%add18 = add nsw i32 %13, 3
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store i32 %add18, ptr %b, align 4
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br label %sw.epilog26
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sw.bb19: ; preds = %sw.epilog10
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%14 = load i32, ptr %b, align 4
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%add20 = add nsw i32 %14, 140
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store i32 %add20, ptr %b, align 4
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br label %sw.bb21
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sw.bb21: ; preds = %sw.epilog10, %sw.epilog10, %sw.bb19
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%15 = load i32, ptr %b, align 4
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%add22 = add nsw i32 %15, 5
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store i32 %add22, ptr %b, align 4
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br label %sw.epilog26
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sw.bb23: ; preds = %sw.epilog10
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br label %sw.bb24
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sw.bb24: ; preds = %sw.epilog10, %sw.bb23
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br label %sw.epilog26
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sw.default25: ; preds = %sw.epilog10
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br label %sw.epilog26
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sw.epilog26: ; preds = %sw.default25, %sw.bb24, %sw.bb21, %sw.bb17, %sw.bb15
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%16 = load i32, ptr %a, align 4
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switch i32 %16, label %sw.epilog29 [
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i32 100, label %sw.bb27
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]
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sw.bb27: ; preds = %sw.epilog26
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%17 = load i32, ptr %b, align 4
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%add28 = add nsw i32 %17, 100
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store i32 %add28, ptr %b, align 4
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br label %sw.epilog29
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sw.epilog29: ; preds = %sw.epilog26, %sw.bb27
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%18 = load i32, ptr %a, align 4
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switch i32 %18, label %sw.default30 [
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]
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sw.default30: ; preds = %sw.epilog29
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%19 = load i32, ptr %b, align 4
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%add31 = add nsw i32 %19, 100
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store i32 %add31, ptr %b, align 4
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%20 = load i32, ptr %c, align 4
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%add32 = add nsw i32 %20, 200
|
|
store i32 %add32, ptr %c, align 4
|
|
br label %sw.epilog33
|
|
|
|
sw.epilog33: ; preds = %sw.default30
|
|
%21 = load i32, ptr %a, align 4
|
|
switch i32 %21, label %sw.epilog45 [
|
|
i32 300, label %sw.bb34
|
|
i32 400, label %sw.bb36
|
|
]
|
|
|
|
sw.bb34: ; preds = %sw.epilog33
|
|
%22 = load i32, ptr %b, align 4
|
|
%add35 = add nsw i32 %22, 300
|
|
store i32 %add35, ptr %b, align 4
|
|
br label %sw.bb36
|
|
|
|
sw.bb36: ; preds = %sw.epilog33, %sw.bb34
|
|
%23 = load i32, ptr %c, align 4
|
|
switch i32 %23, label %sw.epilog44 [
|
|
i32 500, label %sw.bb37
|
|
i32 600, label %sw.bb39
|
|
]
|
|
|
|
sw.bb37: ; preds = %sw.bb36
|
|
%24 = load i32, ptr %b, align 4
|
|
%add38 = add nsw i32 %24, 500
|
|
store i32 %add38, ptr %b, align 4
|
|
br label %sw.epilog44
|
|
|
|
sw.bb39: ; preds = %sw.bb36
|
|
%25 = load i32, ptr %b, align 4
|
|
switch i32 %25, label %sw.default40 [
|
|
]
|
|
|
|
sw.default40: ; preds = %sw.bb39
|
|
%26 = load i32, ptr %a, align 4
|
|
%add41 = add nsw i32 %26, 600
|
|
store i32 %add41, ptr %a, align 4
|
|
%27 = load i32, ptr %b, align 4
|
|
%add42 = add nsw i32 %27, 600
|
|
store i32 %add42, ptr %b, align 4
|
|
br label %sw.epilog43
|
|
|
|
sw.epilog43: ; preds = %sw.default40
|
|
br label %sw.epilog44
|
|
|
|
sw.epilog44: ; preds = %sw.epilog43, %sw.bb36, %sw.bb37
|
|
br label %sw.epilog45
|
|
|
|
sw.epilog45: ; preds = %sw.epilog44, %sw.epilog33
|
|
%28 = load i32, ptr %a, align 4
|
|
%29 = load i32, ptr %b, align 4
|
|
%add46 = add nsw i32 %28, %29
|
|
%30 = load i32, ptr %c, align 4
|
|
%add47 = add nsw i32 %add46, %30
|
|
ret i32 %add47
|
|
}
|
|
|
|
; Function Attrs: convergent noinline norecurse nounwind optnone
|
|
define internal spir_func void @main() #0 {
|
|
entry:
|
|
%0 = call token @llvm.experimental.convergence.entry()
|
|
%call1 = call spir_func noundef i32 @_Z7processv() #3 [ "convergencectrl"(token %0) ]
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: convergent norecurse
|
|
define void @main.1() #2 {
|
|
entry:
|
|
call void @main()
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
|
|
attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
|
|
attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
|
|
attributes #3 = { convergent }
|
|
|
|
!llvm.module.flags = !{!0, !1, !2}
|
|
|
|
|
|
!0 = !{i32 1, !"wchar_size", i32 4}
|
|
!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
|
|
!2 = !{i32 7, !"frame-pointer", i32 2}
|
|
|
|
|