1ed65febd9
This commit adds an initial SPIR-V structurizer. It leverages the previously merged passes, and the convergence region analysis to determine the correct merge and continue blocks for SPIR-V. The first part does a branch cleanup (simplifying switches, and legalizing them), then merge instructions are added to cycles, convergent and later divergent blocks. Then comes the important part: splitting critical edges, and making sure the divergent construct boundaries don't cross. - we split blocks with multiple headers into 2 blocks. - we split blocks that are a merge blocks for 2 or more constructs: SPIR-V spec disallow a merge block to be shared by 2 loop/switch/condition construct. - we split merge & continue blocks: SPIR-V spec disallow a basic block to be both a continue block, and a merge block. - we remove superfluous headers: when a header doesn't bring more info than the parent on the divergence state, it must be removed. This PR leverages the merged SPIR-V simulator for testing, as long as spirv-val. For now, most DXC structurization tests are passing. The unsupported ones are either caused by unsupported features like switches on boolean types, or switches in region exits, because the MergeExit pass doesn't support those yet (there is a FIXME). This PR is quite large, and the addition not trivial, so I tried to keep it simple. E.G: as soon as the CFG changes, I recompute the dominator trees and other structures instead of updating them. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
191 lines
6.7 KiB
LLVM
191 lines
6.7 KiB
LLVM
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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;
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; int foo() { return true; }
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;
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; [numthreads(1, 1, 1)]
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; void main() {
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; int val = 0;
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; int i = 0;
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;
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; while (i < 10) {
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; val = i;
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; if (val > 5) {
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; break;
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; }
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;
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; if (val > 6) {
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; break;
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; break; // No SPIR-V should be emitted for this statement.
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; val++; // No SPIR-V should be emitted for this statement.
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; while(true); // No SPIR-V should be emitted for this statement.
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; --i; // No SPIR-V should be emitted for this statement.
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; }
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; }
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;
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; ////////////////////////////////////////////////////////////////////////////////
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; // Nested while loops with break statements //
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; // Each break statement should branch to the corresponding loop's break block //
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; ////////////////////////////////////////////////////////////////////////////////
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;
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; while (true) {
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; i++;
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; while(i<20) {
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; val = i;
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; {{break;}}
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; }
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; --i;
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; break;
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; }
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; }
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; CHECK: %[[#func_16:]] = OpFunction %[[#uint:]] DontInline %[[#]]
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; CHECK: %[[#bb37:]] = OpLabel
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; CHECK: OpReturnValue %[[#]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_17:]] = OpFunction %[[#void:]] DontInline %[[#]]
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; CHECK: %[[#bb38:]] = OpLabel
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; CHECK: OpBranch %[[#bb39:]]
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; CHECK: %[[#bb39:]] = OpLabel
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; CHECK: OpLoopMerge %[[#bb40:]] %[[#bb41:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb42:]] %[[#bb40:]]
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; CHECK: %[[#bb42:]] = OpLabel
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; CHECK: OpBranchConditional %[[#]] %[[#bb40:]] %[[#bb43:]]
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; CHECK: %[[#bb43:]] = OpLabel
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; CHECK: OpBranchConditional %[[#]] %[[#bb40:]] %[[#bb41:]]
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; CHECK: %[[#bb40:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb44:]] None
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; CHECK: OpSwitch %[[#]] %[[#bb44:]] 1 %[[#bb44:]] 2 %[[#bb44:]]
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; CHECK: %[[#bb41:]] = OpLabel
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; CHECK: OpBranch %[[#bb39:]]
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; CHECK: %[[#bb44:]] = OpLabel
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; CHECK: OpBranch %[[#bb45:]]
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; CHECK: %[[#bb45:]] = OpLabel
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; CHECK: OpBranch %[[#bb46:]]
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; CHECK: %[[#bb46:]] = OpLabel
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; CHECK: OpBranch %[[#bb47:]]
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; CHECK: %[[#bb47:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb48:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb49:]] %[[#bb48:]]
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; CHECK: %[[#bb49:]] = OpLabel
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; CHECK: OpBranch %[[#bb48:]]
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; CHECK: %[[#bb48:]] = OpLabel
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; CHECK: OpBranch %[[#bb50:]]
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; CHECK: %[[#bb50:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_35:]] = OpFunction %[[#void:]] None %[[#]]
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; CHECK: %[[#bb51:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define spir_func noundef i32 @_Z3foov() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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ret i32 1
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.entry() #1
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define internal spir_func void @main() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%val = alloca i32, align 4
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%i = alloca i32, align 4
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store i32 0, ptr %val, align 4
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store i32 0, ptr %i, align 4
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br label %while.cond
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while.cond: ; preds = %if.end4, %entry
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%1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
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%2 = load i32, ptr %i, align 4
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%cmp = icmp slt i32 %2, 10
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br i1 %cmp, label %while.body, label %while.end
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while.body: ; preds = %while.cond
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%3 = load i32, ptr %i, align 4
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store i32 %3, ptr %val, align 4
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%4 = load i32, ptr %val, align 4
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%cmp1 = icmp sgt i32 %4, 5
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %while.body
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br label %while.end
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if.end: ; preds = %while.body
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%5 = load i32, ptr %val, align 4
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%cmp2 = icmp sgt i32 %5, 6
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br i1 %cmp2, label %if.then3, label %if.end4
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if.then3: ; preds = %if.end
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br label %while.end
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if.end4: ; preds = %if.end
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br label %while.cond
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while.end: ; preds = %if.then3, %if.then, %while.cond
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br label %while.cond5
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while.cond5: ; preds = %while.end
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%6 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
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br label %while.body6
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while.body6: ; preds = %while.cond5
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%7 = load i32, ptr %i, align 4
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%inc = add nsw i32 %7, 1
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store i32 %inc, ptr %i, align 4
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br label %while.cond7
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while.cond7: ; preds = %while.body6
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%8 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %6) ]
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%9 = load i32, ptr %i, align 4
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%cmp8 = icmp slt i32 %9, 20
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br i1 %cmp8, label %while.body9, label %while.end10
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while.body9: ; preds = %while.cond7
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%10 = load i32, ptr %i, align 4
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store i32 %10, ptr %val, align 4
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br label %while.end10
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while.end10: ; preds = %while.body9, %while.cond7
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%11 = load i32, ptr %i, align 4
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%dec = add nsw i32 %11, -1
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store i32 %dec, ptr %i, align 4
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br label %while.end11
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while.end11: ; preds = %while.end10
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ret void
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}
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; Function Attrs: convergent norecurse
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define void @main.1() #2 {
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entry:
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call void @main()
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ret void
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.loop() #1
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attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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!llvm.module.flags = !{!0, !1, !2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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!2 = !{i32 7, !"frame-pointer", i32 2}
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