b7e4fba6e5
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
51 lines
2.0 KiB
LLVM
51 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=false | FileCheck %s --check-prefix=NO-POSTRA
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=true | FileCheck %s --check-prefix=POSTRA
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define float @PR35982_emms(<1 x i64>) nounwind {
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; NO-POSTRA-LABEL: PR35982_emms:
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; NO-POSTRA: # %bb.0:
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; NO-POSTRA-NEXT: subl $8, %esp
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; NO-POSTRA-NEXT: movl {{[0-9]+}}(%esp), %eax
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; NO-POSTRA-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; NO-POSTRA-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
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; NO-POSTRA-NEXT: movd %mm0, %ecx
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; NO-POSTRA-NEXT: emms
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; NO-POSTRA-NEXT: movl %eax, (%esp)
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; NO-POSTRA-NEXT: fildl (%esp)
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; NO-POSTRA-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; NO-POSTRA-NEXT: fiaddl {{[0-9]+}}(%esp)
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; NO-POSTRA-NEXT: addl $8, %esp
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; NO-POSTRA-NEXT: retl
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;
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; POSTRA-LABEL: PR35982_emms:
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; POSTRA: # %bb.0:
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; POSTRA-NEXT: subl $8, %esp
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; POSTRA-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; POSTRA-NEXT: movl {{[0-9]+}}(%esp), %eax
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; POSTRA-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
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; POSTRA-NEXT: movd %mm0, %ecx
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; POSTRA-NEXT: emms
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; POSTRA-NEXT: movl %eax, (%esp)
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; POSTRA-NEXT: fildl (%esp)
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; POSTRA-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; POSTRA-NEXT: fiaddl {{[0-9]+}}(%esp)
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; POSTRA-NEXT: addl $8, %esp
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; POSTRA-NEXT: retl
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%2 = bitcast <1 x i64> %0 to <2 x i32>
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%3 = extractelement <2 x i32> %2, i32 0
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%4 = extractelement <1 x i64> %0, i32 0
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%5 = bitcast i64 %4 to <1 x i64>
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%6 = tail call <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64> %5, <1 x i64> %5)
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%7 = bitcast <1 x i64> %6 to <2 x i32>
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%8 = extractelement <2 x i32> %7, i32 0
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tail call void @llvm.x86.mmx.emms()
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%9 = sitofp i32 %3 to float
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%10 = sitofp i32 %8 to float
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%11 = fadd float %9, %10
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ret float %11
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}
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declare <1 x i64> @llvm.x86.mmx.punpckhdq(<1 x i64>, <1 x i64>)
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declare void @llvm.x86.mmx.emms()
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