f673882323
Currently targets without LZCNT/TZCNT won't speculate with BSR/BSF instructions in case they have a zero value input, meaning we always insert a test+branch for the zero-input case. This patch proposes we allow speculation if the target has CMOV, and perform a branchless select instead to handle the zero input case. This will predominately help x86-64 targets where we haven't set any particular cpu target. We already always perform BSR/BSF instructions if we were lowering a CTLZ/CTTZ_ZERO_UNDEF instruction.
26 lines
907 B
LLVM
26 lines
907 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
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define void @PR92569(i64 %arg, <8 x i8> %arg1) {
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; CHECK-LABEL: PR92569:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bsfq %rdi, %rax
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; CHECK-NEXT: movl $64, %ecx
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; CHECK-NEXT: cmovneq %rax, %rcx
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; CHECK-NEXT: shrb $3, %cl
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; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: andl $15, %eax
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; CHECK-NEXT: movzbl -24(%rsp,%rax), %eax
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; CHECK-NEXT: movl %eax, 0
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; CHECK-NEXT: retq
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%cttz = call i64 @llvm.cttz.i64(i64 %arg, i1 false)
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%trunc = trunc i64 %cttz to i8
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%lshr = lshr i8 %trunc, 3
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%extractelement = extractelement <8 x i8> %arg1, i8 %lshr
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%freeze = freeze i8 %extractelement
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%zext = zext i8 %freeze to i32
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store i32 %zext, ptr addrspace(1) null, align 4
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ret void
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}
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