0605e984fa
Prior to this change, `SelectionDAGBuilder` was producing `SDNode`s of the form: `f32 = extract_vector_elt <1 x bfloat|half>, i32 0` when lowering phis of `<1 x bfloat|half>` and running on a target that promotes this type to `f32` (like some x86 or AMDGPU targets.) This construct is invalid since this type of node only allows type extensions for integer types. It went unotice because the `extract_vector_elt` node is later broken down in `bitcast` followed by `bf16_to_fp|fp_extend`. However, when the argument of the phi is a constant we were crashing because the existing code would try to constant fold this `extract_vector_elt` into a any_ext. This patch fixes this by using a proper decomposition for `<1 x bfloat|half>`: ``` bfloat|half = bitcast <1 x blfoat|half> float = fp_extend bfloat|half ``` This change should be NFC for the non-constant-folding cases and fix the SDISel crashes (reported in https://github.com/llvm/llvm-project/issues/94449) for the folding cases. Note: The change on the arm test is a missing fp16 to f32 constant folding exposed by this patch. I'll push a separate improvement for that.
115 lines
3.8 KiB
LLVM
115 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mcpu=generic -mtriple=x86_64-apple-darwin %s -o - | FileCheck %s
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; For all these tests we disable optimizations through function attributes
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; because the code we are exercising here needs phis and we want to keep the
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; IR small.
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; This code used to crash in SDISel because bf16 was promoted to f32 through
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; a `f32 = vector_extract_elt <1 x bf16>, i32 0`, which is illegal.
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; The invalid SDNode and thus, the crash was only exposed by the constant
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; folding.
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define void @phi_vec1bf16_to_f32_with_const_folding(ptr %dst) #0 {
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; CHECK-LABEL: phi_vec1bf16_to_f32_with_const_folding:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rdi, %rbx
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; CHECK-NEXT: jmp LBB0_1
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; CHECK-NEXT: LBB0_1: ## %bb
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: callq ___truncsfbf2
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; CHECK-NEXT: pextrw $0, %xmm0, %eax
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; CHECK-NEXT: movw %ax, 2(%rbx)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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entry:
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br label %bb
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bb:
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%phi = phi <1 x bfloat> [ zeroinitializer, %entry ]
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%res = shufflevector <1 x bfloat> poison, <1 x bfloat> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x bfloat> %res, ptr %dst
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ret void
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}
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; Same as phi_vec1bf16_to_f32_with_const_folding but without the constant
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; folding.
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; This test exercises the same invalid SDNode, but it happened to work by
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; accident before. Here we make sure the fix also work as expected in the
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; non-constant folding case.
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define void @phi_vec1bf16_to_f32(ptr %src, ptr %dst) #0 {
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; CHECK-LABEL: phi_vec1bf16_to_f32:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset %rbx, -16
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; CHECK-NEXT: movq %rsi, %rbx
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: shll $16, %eax
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; CHECK-NEXT: movd %eax, %xmm0
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; CHECK-NEXT: jmp LBB1_1
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; CHECK-NEXT: LBB1_1: ## %bb
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; CHECK-NEXT: callq ___truncsfbf2
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; CHECK-NEXT: pextrw $0, %xmm0, %eax
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; CHECK-NEXT: movw %ax, 2(%rbx)
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: retq
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entry:
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%input = load <1 x bfloat>, ptr %src
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br label %bb
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bb:
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%phi = phi <1 x bfloat> [ %input, %entry ]
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%res = shufflevector <1 x bfloat> poison, <1 x bfloat> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x bfloat> %res, ptr %dst
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ret void
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}
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; Half type is legal on x86 so nothing special here, but it
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; doesn't hurt to be thorough.
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define void @phi_vec1half_with_const_folding(ptr %dst) #0 {
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; CHECK-LABEL: phi_vec1half_with_const_folding:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: jmp LBB2_1
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; CHECK-NEXT: LBB2_1: ## %bb
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; CHECK-NEXT: pextrw $0, %xmm0, %eax
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; CHECK-NEXT: movw %ax, 2(%rdi)
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; CHECK-NEXT: retq
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entry:
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br label %bb
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bb:
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%phi = phi <1 x half> [ zeroinitializer, %entry ]
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%res = shufflevector <1 x half> poison, <1 x half> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x half> %res, ptr %dst
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ret void
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}
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; Half type is legal on x86 so nothing special here, but it
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; doesn't hurt to be thorough.
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; Same as phi_vec1half_with_constant_folding but without the constant folding.
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define void @phi_vec1half(ptr %src, ptr %dst) #0 {
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; CHECK-LABEL: phi_vec1half:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: pinsrw $0, (%rdi), %xmm0
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; CHECK-NEXT: jmp LBB3_1
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; CHECK-NEXT: LBB3_1: ## %bb
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; CHECK-NEXT: pextrw $0, %xmm0, %eax
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; CHECK-NEXT: movw %ax, 2(%rsi)
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; CHECK-NEXT: retq
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entry:
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%input = load <1 x half>, ptr %src
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br label %bb
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bb:
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%phi = phi <1 x half> [ %input, %entry ]
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%res = shufflevector <1 x half> poison, <1 x half> %phi, <2 x i32> <i32 0, i32 1>
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store <2 x half> %res, ptr %dst
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ret void
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}
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attributes #0 = { noinline optnone }
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