1f2a634c44
Motivating example: https://godbolt.org/z/eb97zrxhx Here we have 2 induction variables in the loop: one is corresponding to i variable (add rdx, 4), the other - to res (add rax, 2). The second induction variable can be removed by rewriteLoopExitValues() method (final value of res at loop exit is unroll_iter * -2); however, this doesn't happen because we have duplicated LCSSA phi nodes at loop exit: ``` ; Preheader: for.body.preheader.new: ; preds = %for.body.preheader %unroll_iter = and i64 %N, -4 br label %for.body ; Loop: for.body: ; preds = %for.body, %for.body.preheader.new %lsr.iv = phi i64 [ %lsr.iv.next, %for.body ], [ 0, %for.body.preheader.new ] %i.07 = phi i64 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ] %inc.3 = add nuw i64 %i.07, 4 %lsr.iv.next = add nsw i64 %lsr.iv, -2 %niter.ncmp.3.not = icmp eq i64 %unroll_iter, %inc.3 br i1 %niter.ncmp.3.not, label %for.end.loopexit.unr-lcssa.loopexit, label %for.body, !llvm.loop !7 ; Exit blocks for.end.loopexit.unr-lcssa.loopexit: ; preds = %for.body %inc.3.lcssa = phi i64 [ %inc.3, %for.body ] %lsr.iv.next.lcssa11 = phi i64 [ %lsr.iv.next, %for.body ] %lsr.iv.next.lcssa = phi i64 [ %lsr.iv.next, %for.body ] br label %for.end.loopexit.unr-lcssa ``` rewriteLoopExitValues requires %lsr.iv.next value to have only 2 uses: one in LCSSA phi node, the other - in induction phi node. Here we have 3 uses of this value because of duplicated lcssa nodes, so the transform doesn't apply and leads to an extra add operation inside the loop. The proposed solution is to accumulate inserted instructions that will require LCSSA form update into SetVector and then call formLCSSAForInstructions for this SetVector once, so the same instructions don't process twice. Reland fixes the issue with preserve-lcssa.ll test: it fails in the situation when x86_64-unknown-linux-gnu target is unavailable in opt. The changes are moved into separate duplicated-phis.ll test with explicit x86 target requirement to fix bots which are not building this target.
76 lines
3.2 KiB
LLVM
76 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-reduce %s -S | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.15.0"
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; Tests for crashes during SCEV expansion.
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%struct.hoge = type { i32, i32, i32, i32 }
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define i64 @blam(ptr %start, ptr %end, ptr %ptr.2) {
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; CHECK-LABEL: @blam(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[START1:%.*]] = ptrtoint ptr [[START:%.*]] to i64
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; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]]
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; CHECK: loop.1.header:
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; CHECK-NEXT: [[LSR_IV4:%.*]] = phi i64 [ [[LSR_IV_NEXT5:%.*]], [[LOOP_1_HEADER]] ], [ [[START1]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[IV_NEXT:%.*]], [[LOOP_1_HEADER]] ], [ [[START]], [[ENTRY]] ]
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; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds [[STRUCT_HOGE:%.*]], ptr [[IV]], i64 1
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; CHECK-NEXT: [[LSR_IV_NEXT5]] = add nuw i64 [[LSR_IV4]], 16
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; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[IV_NEXT]], [[END:%.*]]
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; CHECK-NEXT: br i1 [[EC]], label [[LOOP_2_PH:%.*]], label [[LOOP_1_HEADER]]
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; CHECK: loop.2.ph:
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; CHECK-NEXT: [[LSR_IV_NEXT5_LCSSA:%.*]] = phi i64 [ [[LSR_IV_NEXT5]], [[LOOP_1_HEADER]] ]
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; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi ptr [ [[IV_NEXT]], [[LOOP_1_HEADER]] ]
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; CHECK-NEXT: br label [[LOOP_2_HEADER:%.*]]
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; CHECK: loop.2.header:
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; CHECK-NEXT: [[LSR_IV2:%.*]] = phi i64 [ [[LSR_IV_NEXT3:%.*]], [[LOOP_2_LATCH:%.*]] ], [ [[LSR_IV_NEXT5_LCSSA]], [[LOOP_2_PH]] ]
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; CHECK-NEXT: [[IV2:%.*]] = phi ptr [ [[IV2_NEXT:%.*]], [[LOOP_2_LATCH]] ], [ [[IV_NEXT_LCSSA]], [[LOOP_2_PH]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LSR_IV2]], 12
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; CHECK-NEXT: call void @use.i64(i64 [[TMP0]])
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[IV2]], i64 8
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; CHECK-NEXT: store i32 10, ptr [[SCEVGEP]], align 8
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; CHECK-NEXT: [[EC_2:%.*]] = icmp ugt ptr [[IV2]], [[PTR_2:%.*]]
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; CHECK-NEXT: br i1 [[EC_2]], label [[LOOP_2_EXIT:%.*]], label [[LOOP_2_LATCH]]
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; CHECK: loop.2.latch:
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; CHECK-NEXT: [[IV2_NEXT]] = getelementptr inbounds [[STRUCT_HOGE]], ptr [[IV2]], i64 1
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; CHECK-NEXT: [[LSR_IV_NEXT3]] = add i64 [[LSR_IV2]], 16
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; CHECK-NEXT: br label [[LOOP_2_HEADER]]
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; CHECK: loop.2.exit:
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; CHECK-NEXT: ret i64 [[LSR_IV2]]
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;
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entry:
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br label %loop.1.header
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loop.1.header:
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%iv = phi ptr [ %iv.next, %loop.1.header ], [ %start, %entry ]
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%iv.next = getelementptr inbounds %struct.hoge, ptr %iv, i64 1
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%ec = icmp eq ptr %iv.next, %end
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br i1 %ec, label %loop.2.ph, label %loop.1.header
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loop.2.ph:
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br label %loop.2.header
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loop.2.header:
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%iv2 = phi ptr [ %iv2.next, %loop.2.latch ], [ %iv.next, %loop.2.ph ]
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%tmp7 = getelementptr inbounds %struct.hoge, ptr %iv2, i64 0, i32 3
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%tmp8 = ptrtoint ptr %tmp7 to i64
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call void @use.i64(i64 %tmp8)
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%tmp9 = getelementptr inbounds %struct.hoge, ptr %iv2, i64 0, i32 2
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store i32 10, ptr %tmp9, align 8
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%ec.2 = icmp ugt ptr %iv2, %ptr.2
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br i1 %ec.2, label %loop.2.exit, label %loop.2.latch
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loop.2.latch:
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%iv2.next = getelementptr inbounds %struct.hoge, ptr %iv2, i64 1
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br label %loop.2.header
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loop.2.exit: ; preds = %bb6
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%iv2.cast = ptrtoint ptr %iv2 to i64
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ret i64 %iv2.cast
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}
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declare void @use.i64(i64)
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