68ed1728bf
Unify logic for mayWriteToMemory and mayHaveSideEffects for VPInstruction, with the later relying on the former. Also extend to handle binary operators. Split off from https://github.com/llvm/llvm-project/pull/106441
96 lines
4.8 KiB
LLVM
96 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -mcpu=skylake-avx512 -S %s | FileCheck %s
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target triple = "x86_64-unknown-linux-gnu"
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define i64 @test_pr98660(ptr %dst, i64 %N) {
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; CHECK-LABEL: define i64 @test_pr98660(
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; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 32
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP1]], 1
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP9]], i32 0
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i32 8
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; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[TMP9]], i32 16
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP9]], i32 24
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i32>, ptr [[TMP13]], align 4
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; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <8 x i32>, ptr [[TMP14]], align 4
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; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <8 x i32>, ptr [[TMP15]], align 4
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; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i32>, ptr [[TMP16]], align 4
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; CHECK-NEXT: [[TMP17:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD]], zeroinitializer
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; CHECK-NEXT: [[TMP18:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD1]], zeroinitializer
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; CHECK-NEXT: [[TMP19:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD2]], zeroinitializer
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; CHECK-NEXT: [[TMP20:%.*]] = icmp eq <8 x i32> [[WIDE_LOAD3]], zeroinitializer
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; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP13]], i32 4, <8 x i1> [[TMP17]])
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; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP14]], i32 4, <8 x i1> [[TMP18]])
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; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP15]], i32 4, <8 x i1> [[TMP19]])
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; CHECK-NEXT: call void @llvm.masked.store.v8i32.p0(<8 x i32> zeroinitializer, ptr [[TMP16]], i32 4, <8 x i1> [[TMP20]])
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
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; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
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; CHECK-NEXT: [[IND_ESCAPE:%.*]] = sub i64 [[N_VEC]], 1
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
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; CHECK: [[LOOP_HEADER]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; CHECK-NEXT: [[OR:%.*]] = or disjoint i64 [[IV]], 1
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[OR]]
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0
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; CHECK-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
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; CHECK: [[THEN]]:
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; CHECK-NEXT: store i32 0, ptr [[GEP]], align 4
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; CHECK-NEXT: br label %[[LOOP_LATCH]]
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; CHECK: [[LOOP_LATCH]]:
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV]], [[N]]
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; CHECK-NEXT: br i1 [[EC]], label %[[LOOP_HEADER]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RET:%.*]] = phi i64 [ [[IV]], %[[LOOP_LATCH]] ], [ [[IND_ESCAPE]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i64 [[RET]]
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%or = or disjoint i64 %iv, 1
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%gep = getelementptr i32, ptr %dst, i64 %or
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%l = load i32, ptr %gep
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%c = icmp eq i32 %l, 0
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br i1 %c, label %then, label %loop.latch
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then:
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store i32 0, ptr %gep, align 4
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br label %loop.latch
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loop.latch:
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%iv.next = add i64 %iv, 1
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%ec = icmp ult i64 %iv, %N
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br i1 %ec, label %loop.header, label %exit
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exit:
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%ret = phi i64 [ %iv, %loop.latch ]
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ret i64 %ret
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}
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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;.
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