8ec406757c
This patch implements explicit unrolling by UF as VPlan transform. In follow up patches this will allow simplifying VPTransform state (no need to store unrolled parts) as well as recipe execution (no need to generate code for multiple parts in an each recipe). It also allows for more general optimziations (e.g. avoid generating code for recipes that are uniform-across parts). It also unifies the logic dealing with unrolled parts in a single place, rather than spreading it out across multiple places (e.g. VPlan post processing for header-phi recipes previously.) In the initial implementation, a number of recipes still take the unrolled part as additional, optional argument, if their execution depends on the unrolled part. The computation for start/step values for scalable inductions changed slightly. Previously the step would be computed as scalar and then splatted, now vscale gets splatted and multiplied by the step in a vector mul. This has been split off https://github.com/llvm/llvm-project/pull/94339 which also includes changes to simplify VPTransfomState and recipes' ::execute. The current version mostly leaves existing ::execute untouched and instead sets VPTransfomState::UF to 1. A follow-up patch will clean up all references to VPTransformState::UF. Another follow-up patch will simplify VPTransformState to only store a single vector value per VPValue. PR: https://github.com/llvm/llvm-project/pull/95842
129 lines
4.4 KiB
LLVM
129 lines
4.4 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -p loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -debug -disable-output %s 2>&1 | FileCheck %s
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define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
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; CHECK: VPlan 'Final VPlan for VF={2},UF={1}' {
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; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
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; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count
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; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<entry>:
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; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV ((-1 * (ptrtoint ptr %start to i64)) + (ptrtoint ptr %end to i64))
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: vector.ph:
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; CHECK-NEXT: Successor(s): vector loop
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; CHECK-EMPTY:
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; CHECK-NEXT: <x1> vector loop: {
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; CHECK-NEXT: vector.body:
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; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
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; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
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; CHECK-NEXT: EMIT vp<[[PTR:%.+]]> = ptradd ir<%start>, vp<[[STEPS]]>
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; CHECK-NEXT: vp<[[WIDE_PTR:%.+]]> = vector-pointer vp<[[PTR]]>
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; CHECK-NEXT: WIDEN ir<%l> = load vp<[[WIDE_PTR]]>
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; CHECK-NEXT: EMIT vp<[[C1:%.+]]> = icmp eq ir<%l>, ir<-12>
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; CHECK-NEXT: EMIT vp<[[C2:%.+]]> = icmp eq ir<%l>, ir<13>
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; CHECK-NEXT: EMIT vp<[[OR_CASES:%.+]]> = or vp<[[C1]]>, vp<[[C2]]>
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; CHECK-NEXT: EMIT vp<[[DEFAULT_MASK:%.+]]> = not vp<[[OR_CASES]]>
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; CHECK-NEXT: Successor(s): pred.store
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.store: {
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; CHECK-NEXT: pred.store.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[C2]]>
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; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.if:
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; CHECK-NEXT: REPLICATE store ir<0>, vp<[[PTR]]>
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; CHECK-NEXT: Successor(s): pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.continue:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): if.then.2.0
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; CHECK-EMPTY:
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; CHECK-NEXT: if.then.2.0:
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; CHECK-NEXT: Successor(s): pred.store
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.store: {
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; CHECK-NEXT: pred.store.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[C1]]>
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; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.if:
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; CHECK-NEXT: REPLICATE store ir<42>, vp<[[PTR]]>
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; CHECK-NEXT: Successor(s): pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.continue:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): if.then.1.1
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; CHECK-EMPTY:
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; CHECK-NEXT: if.then.1.1:
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; CHECK-NEXT: Successor(s): pred.store
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; CHECK-EMPTY:
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; CHECK-NEXT: <xVFxUF> pred.store: {
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; CHECK-NEXT: pred.store.entry:
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; CHECK-NEXT: BRANCH-ON-MASK vp<[[DEFAULT_MASK]]>
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; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.if:
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; CHECK-NEXT: REPLICATE store ir<2>, vp<[[PTR]]>
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; CHECK-NEXT: Successor(s): pred.store.continue
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; CHECK-EMPTY:
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; CHECK-NEXT: pred.store.continue:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): default.2
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; CHECK-EMPTY:
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; CHECK-NEXT: default.2:
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; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
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; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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; CHECK-NEXT: Successor(s): middle.block
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; CHECK-EMPTY:
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; CHECK-NEXT: middle.block:
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; CHECK-NEXT: EMIT vp<[[MIDDLE_CMP:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]>
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; CHECK-NEXT: EMIT branch-on-cond vp<[[MIDDLE_CMP]]>
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; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
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; CHECK-EMPTY:
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; CHECK-NEXT: ir-bb<exit>:
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; CHECK-NEXT: No successors
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; CHECK-EMPTY:
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; CHECK-NEXT: scalar.ph:
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; CHECK-NEXT: No successors
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; CHECK-NEXT: }
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;
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entry:
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br label %loop.header
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loop.header:
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%ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
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%l = load i8, ptr %ptr.iv, align 1
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switch i8 %l, label %default [
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i8 -12, label %if.then.1
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i8 13, label %if.then.2
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i8 0, label %default
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]
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if.then.1:
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store i8 42, ptr %ptr.iv, align 1
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br label %loop.latch
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if.then.2:
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store i8 0, ptr %ptr.iv, align 1
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br label %loop.latch
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default:
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store i8 2, ptr %ptr.iv, align 1
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br label %loop.latch
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loop.latch:
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%ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 1
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%ec = icmp eq ptr %ptr.iv.next, %end
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br i1 %ec, label %exit, label %loop.header
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exit:
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ret void
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}
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