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a78861fc55d18046989ff4d624a037e9181da170
clang-p2996/llvm/test/Transforms/PhaseOrdering/AArch64
History
David Green 577c7dd7cc [AArch64] Add a phase-ordering test for vectorizing predicated selects. NFC
2024-10-25 15:20:24 +01:00
..
constraint-elimination-placement.ll
[InstCombine] Replace all dominated uses of condition with constants (#105510)
2024-09-01 09:49:23 +08:00
extra-unroll-simplifications.ll
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globals-aa-required-for-vectorization.ll
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hoist-runtime-checks.ll
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hoisting-sinking-required-for-vectorization.ll
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indvars-vectorization.ll
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interleavevectorization.ll
[VPlan] Use pointer to member 0 as VPInterleaveRecipe's pointer arg. (#106431)
2024-10-06 22:53:13 +01:00
lit.local.cfg
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loopflatten.ll
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matrix-extract-insert.ll
[InstCombine] Set samesign when converting signed predicates into unsigned (#112642)
2024-10-17 20:43:48 +08:00
mul-ov.ll
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peel-multiple-unreachable-exits-for-vectorization.ll
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predicated-reduction.ll
[AArch64] Add a phase-ordering test for vectorizing predicated selects. NFC
2024-10-25 15:20:24 +01:00
quant_4x4.ll
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sinking-vs-if-conversion.ll
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slpordering.ll
Revert "[SLP]Initial non-power-of-2 support (but still whole register) for reductions"
2024-10-21 13:37:44 +01:00
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