4b1b51ac52
Enables initial non-power-of-2 support (but still requires number of elements, forming whole registers) for reductions. Enables extra vectorization for MultiSource/Benchmarks/7zip/7zip-benchmark, CINT2006/464.h264ref and CFP2017rate/526.blender_r (checked for SSE2) Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/112361
71 lines
4.1 KiB
LLVM
71 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -mtriple=arm64-apple-ios -S %s | FileCheck --check-prefixes=CHECK,NON-POWER-OF-2 %s
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; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -mtriple=arm64-apple-ios -S %s | FileCheck --check-prefixes=CHECK,POWER-OF-2 %s
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define void @vec3_vectorize_call(ptr %Colour, float %0) {
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; NON-POWER-OF-2-LABEL: @vec3_vectorize_call(
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; NON-POWER-OF-2-NEXT: entry:
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; NON-POWER-OF-2-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[COLOUR:%.*]], align 4
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; NON-POWER-OF-2-NEXT: [[TMP2:%.*]] = insertelement <3 x float> poison, float [[TMP0:%.*]], i32 2
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; NON-POWER-OF-2-NEXT: [[TMP4:%.*]] = call <3 x float> @llvm.vector.insert.v3f32.v2f32(<3 x float> [[TMP2]], <2 x float> [[TMP1]], i64 0)
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; NON-POWER-OF-2-NEXT: [[TMP5:%.*]] = call <3 x float> @llvm.fmuladd.v3f32(<3 x float> [[TMP4]], <3 x float> zeroinitializer, <3 x float> zeroinitializer)
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; NON-POWER-OF-2-NEXT: store <3 x float> [[TMP5]], ptr [[COLOUR]], align 4
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; NON-POWER-OF-2-NEXT: ret void
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;
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; POWER-OF-2-LABEL: @vec3_vectorize_call(
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; POWER-OF-2-NEXT: entry:
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; POWER-OF-2-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[COLOUR:%.*]], align 4
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; POWER-OF-2-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[TMP1]], <2 x float> zeroinitializer, <2 x float> zeroinitializer)
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; POWER-OF-2-NEXT: store <2 x float> [[TMP2]], ptr [[COLOUR]], align 4
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; POWER-OF-2-NEXT: [[ARRAYIDX99_I1:%.*]] = getelementptr float, ptr [[COLOUR]], i64 2
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; POWER-OF-2-NEXT: [[TMP3:%.*]] = call float @llvm.fmuladd.f32(float [[TMP0:%.*]], float 0.000000e+00, float 0.000000e+00)
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; POWER-OF-2-NEXT: store float [[TMP3]], ptr [[ARRAYIDX99_I1]], align 4
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; POWER-OF-2-NEXT: ret void
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;
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entry:
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%1 = load float, ptr %Colour, align 4
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%2 = call float @llvm.fmuladd.f32(float %1, float 0.000000e+00, float 0.000000e+00)
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store float %2, ptr %Colour, align 4
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%arrayidx91.i = getelementptr float, ptr %Colour, i64 1
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%3 = load float, ptr %arrayidx91.i, align 4
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%4 = call float @llvm.fmuladd.f32(float %3, float 0.000000e+00, float 0.000000e+00)
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store float %4, ptr %arrayidx91.i, align 4
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%arrayidx99.i1 = getelementptr float, ptr %Colour, i64 2
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%5 = call float @llvm.fmuladd.f32(float %0, float 0.000000e+00, float 0.000000e+00)
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store float %5, ptr %arrayidx99.i1, align 4
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ret void
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}
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define void @vec3_fmuladd_64(ptr %Colour, double %0) {
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; CHECK-LABEL: @vec3_fmuladd_64(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ARRAYIDX80:%.*]] = getelementptr float, ptr [[COLOUR:%.*]], i64 2
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[TMP0:%.*]], i32 0
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP2]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
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; CHECK-NEXT: [[TMP4:%.*]] = fptrunc <2 x double> [[TMP3]] to <2 x float>
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; CHECK-NEXT: store <2 x float> [[TMP4]], ptr [[COLOUR]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = call double @llvm.fmuladd.f64(double [[TMP0]], double 0.000000e+00, double 0.000000e+00)
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; CHECK-NEXT: [[CONV82:%.*]] = fptrunc double [[TMP5]] to float
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; CHECK-NEXT: store float [[CONV82]], ptr [[ARRAYIDX80]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%arrayidx72 = getelementptr float, ptr %Colour, i64 1
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%arrayidx80 = getelementptr float, ptr %Colour, i64 2
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%1 = call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double 0.000000e+00)
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%conv66 = fptrunc double %1 to float
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store float %conv66, ptr %Colour, align 4
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%2 = call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double 0.000000e+00)
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%conv74 = fptrunc double %2 to float
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store float %conv74, ptr %arrayidx72, align 4
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%3 = call double @llvm.fmuladd.f64(double %0, double 0.000000e+00, double 0.000000e+00)
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%conv82 = fptrunc double %3 to float
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store float %conv82, ptr %arrayidx80, align 4
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ret void
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}
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declare float @llvm.fmuladd.f32(float, float, float)
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declare double @llvm.fmuladd.f64(double, double, double)
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