74ca67c109
Whether an instruction is deemed to have side effects in determined by whether it has a tblgen pattern that emits a single instruction. Because of the way a lot of the the vcvt instructions are specified either in dagtodag code or with patterns that emit multiple instructions, they don't get marked as not having side effects. This just marks them as not having side effects manually. It can help especially with instruction scheduling, to not create artificial barriers, but one of these tests also managed to produce fewer instructions. Differential Revision: https://reviews.llvm.org/D81639
47 lines
2.1 KiB
LLVM
47 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD
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define half @foo(half %a, half %b) {
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; SOFT-LABEL: foo:
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; SOFT: @ %bb.0: @ %entry
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; SOFT-NEXT: vmov s0, r0
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; SOFT-NEXT: vmov s2, r1
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; SOFT-NEXT: vcvtb.f32.f16 s0, s0
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; SOFT-NEXT: vcvtb.f32.f16 s2, s2
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; SOFT-NEXT: vadd.f32 s0, s0, s2
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; SOFT-NEXT: vcvtb.f16.f32 s0, s0
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; SOFT-NEXT: vmov r0, s0
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; SOFT-NEXT: bx lr
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;
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; HARD-LABEL: foo:
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; HARD: @ %bb.0: @ %entry
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; HARD-NEXT: vcvtb.f32.f16 s2, s1
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; HARD-NEXT: vcvtb.f32.f16 s0, s0
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; HARD-NEXT: vadd.f32 s0, s0, s2
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; HARD-NEXT: vcvtb.f16.f32 s0, s0
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; HARD-NEXT: bx lr
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;
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; FULL-SOFT-LABEL: foo:
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; FULL-SOFT: @ %bb.0: @ %entry
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; FULL-SOFT-NEXT: vmov.f16 s0, r1
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; FULL-SOFT-NEXT: vmov.f16 s2, r0
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; FULL-SOFT-NEXT: vadd.f16 s0, s2, s0
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; FULL-SOFT-NEXT: vmov r0, s0
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; FULL-SOFT-NEXT: bx lr
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;
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; FULL-HARD-LABEL: foo:
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; FULL-HARD: @ %bb.0: @ %entry
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; FULL-HARD-NEXT: vadd.f16 s0, s0, s1
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; FULL-HARD-NEXT: bx lr
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entry:
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%0 = fadd half %a, %b
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ret half %0
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}
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