8d5e974076
Summary: Using HI here makes no logical sense, since the dword is only 32 bits to begin with. Current Mesa master does not look at the relocation type at all, so this change is fine. Future Mesa will rely on this, however. Change-Id: I91085707834c4ac0370926602b93c94b90e44cb1 Reviewers: arsenm, rampitec, mareko Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D55369 llvm-svn: 349620
91 lines
2.9 KiB
C++
91 lines
2.9 KiB
C++
//===- AMDGPUELFObjectWriter.cpp - AMDGPU ELF Writer ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUMCTargetDesc.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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namespace {
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class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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AMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend);
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protected:
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unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
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const MCFixup &Fixup, bool IsPCRel) const override;
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};
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} // end anonymous namespace
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AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit,
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uint8_t OSABI,
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bool HasRelocationAddend)
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: MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_AMDGPU,
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HasRelocationAddend) {}
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unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
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const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const {
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if (const auto *SymA = Target.getSymA()) {
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// SCRATCH_RSRC_DWORD[01] is a special global variable that represents
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// the scratch buffer.
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if (SymA->getSymbol().getName() == "SCRATCH_RSRC_DWORD0" ||
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SymA->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
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return ELF::R_AMDGPU_ABS32_LO;
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}
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switch (Target.getAccessVariant()) {
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default:
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break;
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case MCSymbolRefExpr::VK_GOTPCREL:
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return ELF::R_AMDGPU_GOTPCREL;
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case MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_LO:
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return ELF::R_AMDGPU_GOTPCREL32_LO;
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case MCSymbolRefExpr::VK_AMDGPU_GOTPCREL32_HI:
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return ELF::R_AMDGPU_GOTPCREL32_HI;
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case MCSymbolRefExpr::VK_AMDGPU_REL32_LO:
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return ELF::R_AMDGPU_REL32_LO;
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case MCSymbolRefExpr::VK_AMDGPU_REL32_HI:
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return ELF::R_AMDGPU_REL32_HI;
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case MCSymbolRefExpr::VK_AMDGPU_REL64:
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return ELF::R_AMDGPU_REL64;
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}
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switch (Fixup.getKind()) {
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default: break;
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case FK_PCRel_4:
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return ELF::R_AMDGPU_REL32;
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case FK_Data_4:
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case FK_SecRel_4:
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return ELF::R_AMDGPU_ABS32;
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case FK_Data_8:
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return ELF::R_AMDGPU_ABS64;
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}
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llvm_unreachable("unhandled relocation type");
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}
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std::unique_ptr<MCObjectTargetWriter>
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llvm::createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
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bool HasRelocationAddend) {
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return llvm::make_unique<AMDGPUELFObjectWriter>(Is64Bit, OSABI,
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HasRelocationAddend);
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}
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