9a0ed20072
When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8. Since there are already multiple IIC for store update, this patch also merge IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU IIC_LdStSTDUX to IIC_LdStSTUX and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference. Differential Revision: https://reviews.llvm.org/D54700 llvm-svn: 347311
171 lines
7.8 KiB
TableGen
171 lines
7.8 KiB
TableGen
//===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Primary reference:
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// A2 Processor User's Manual.
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// IBM (as updated in) 2010.
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//===----------------------------------------------------------------------===//
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// Functional units on the PowerPC A2 chip sets
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//
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def A2_XU : FuncUnit; // A2_XU pipeline
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def A2_FU : FuncUnit; // FI pipeline
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//
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// This file defines the itinerary class data for the PPC A2 processor.
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//
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//===----------------------------------------------------------------------===//
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def PPCA2Itineraries : ProcessorItineraries<
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[A2_XU, A2_FU], [], [
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InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
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[1, 0, 0]>,
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InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
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[2, 0, 0]>,
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InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>],
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[2, 0, 0, 0]>,
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InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
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[2, 0, 0]>,
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InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
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[39, 0, 0]>,
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InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
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[71, 0, 0]>,
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InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
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[5, 0, 0]>,
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InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
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[5, 0, 0]>,
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InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
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[2, 0, 0]>,
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InstrItinData<IIC_IntRotateD, [InstrStage<1, [A2_XU]>],
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[2, 0, 0]>,
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InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>],
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[2, 0, 0]>,
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InstrItinData<IIC_IntShift, [InstrStage<1, [A2_XU]>],
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[2, 0, 0]>,
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InstrItinData<IIC_IntTrapW, [InstrStage<1, [A2_XU]>],
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[2, 0]>,
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InstrItinData<IIC_IntTrapD, [InstrStage<1, [A2_XU]>],
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[2, 0]>,
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InstrItinData<IIC_BrB, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_BrCR, [InstrStage<1, [A2_XU]>],
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[1, 0, 0]>,
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InstrItinData<IIC_BrMCR, [InstrStage<1, [A2_XU]>],
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[5, 0, 0]>,
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InstrItinData<IIC_BrMCRX, [InstrStage<1, [A2_XU]>],
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[1, 0, 0]>,
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InstrItinData<IIC_LdStDCBA, [InstrStage<1, [A2_XU]>],
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[1, 0, 0]>,
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InstrItinData<IIC_LdStDCBF, [InstrStage<1, [A2_XU]>],
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[1, 0, 0]>,
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InstrItinData<IIC_LdStDCBI, [InstrStage<1, [A2_XU]>],
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[1, 0, 0]>,
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InstrItinData<IIC_LdStLoad, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>],
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLDU, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_LdStLDUX, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_LdStStore, [InstrStage<1, [A2_XU]>],
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[0, 0, 0]>,
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InstrItinData<IIC_LdStICBI, [InstrStage<1, [A2_XU]>],
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[16, 0, 0]>,
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InstrItinData<IIC_LdStSTFD, [InstrStage<1, [A2_XU]>],
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[0, 0, 0]>,
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InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [A2_XU]>],
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[2, 0, 0, 0]>,
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InstrItinData<IIC_LdStLFD, [InstrStage<1, [A2_XU]>],
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[7, 0, 0]>,
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InstrItinData<IIC_LdStLFDU, [InstrStage<1, [A2_XU]>],
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[7, 9, 0, 0]>,
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InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [A2_XU]>],
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[7, 9, 0, 0]>,
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InstrItinData<IIC_LdStLHA, [InstrStage<1, [A2_XU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_LdStLHAU, [InstrStage<1, [A2_XU]>],
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [A2_XU]>],
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[6, 8, 0, 0]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [A2_XU]>],
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[82, 0, 0]>, // L2 latency
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InstrItinData<IIC_LdStSTD, [InstrStage<1, [A2_XU]>],
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[0, 0, 0]>,
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InstrItinData<IIC_LdStSTU, [InstrStage<1, [A2_XU]>],
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[2, 0, 0, 0]>,
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InstrItinData<IIC_LdStSTUX, [InstrStage<1, [A2_XU]>],
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[2, 0, 0, 0]>,
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InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [A2_XU]>],
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[82, 0, 0]>, // L2 latency
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InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [A2_XU]>],
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[82, 0, 0]>, // L2 latency
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InstrItinData<IIC_LdStSync, [InstrStage<1, [A2_XU]>],
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[6]>,
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InstrItinData<IIC_SprISYNC, [InstrStage<1, [A2_XU]>],
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[16]>,
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InstrItinData<IIC_SprMTMSR, [InstrStage<1, [A2_XU]>],
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[16, 0]>,
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InstrItinData<IIC_SprMFCR, [InstrStage<1, [A2_XU]>],
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[6, 0]>,
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InstrItinData<IIC_SprMFCRF, [InstrStage<1, [A2_XU]>],
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[1, 0]>,
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InstrItinData<IIC_SprMFMSR, [InstrStage<1, [A2_XU]>],
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[4, 0]>,
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InstrItinData<IIC_SprMFSPR, [InstrStage<1, [A2_XU]>],
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[6, 0]>,
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InstrItinData<IIC_SprMFTB, [InstrStage<1, [A2_XU]>],
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[4, 0]>,
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InstrItinData<IIC_SprMTSPR, [InstrStage<1, [A2_XU]>],
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[6, 0]>,
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InstrItinData<IIC_SprRFI, [InstrStage<1, [A2_XU]>],
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[16]>,
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InstrItinData<IIC_SprSC, [InstrStage<1, [A2_XU]>],
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[16]>,
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InstrItinData<IIC_FPGeneral, [InstrStage<1, [A2_FU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_FPAddSub, [InstrStage<1, [A2_FU]>],
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[6, 0, 0]>,
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InstrItinData<IIC_FPCompare, [InstrStage<1, [A2_FU]>],
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[5, 0, 0]>,
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InstrItinData<IIC_FPDivD, [InstrStage<1, [A2_FU]>],
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[72, 0, 0]>,
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InstrItinData<IIC_FPDivS, [InstrStage<1, [A2_FU]>],
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[59, 0, 0]>,
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InstrItinData<IIC_FPSqrtD, [InstrStage<1, [A2_FU]>],
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[69, 0, 0]>,
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InstrItinData<IIC_FPSqrtS, [InstrStage<1, [A2_FU]>],
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[65, 0, 0]>,
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InstrItinData<IIC_FPFused, [InstrStage<1, [A2_FU]>],
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[6, 0, 0, 0]>,
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InstrItinData<IIC_FPRes, [InstrStage<1, [A2_FU]>],
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[6, 0]>
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]>;
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// ===---------------------------------------------------------------------===//
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// A2 machine model for scheduling and other instruction cost heuristics.
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def PPCA2Model : SchedMachineModel {
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let IssueWidth = 1; // 1 instruction is dispatched per cycle.
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let LoadLatency = 6; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 13;
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let CompleteModel = 0;
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let Itineraries = PPCA2Itineraries;
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}
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