2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
305 lines
11 KiB
C++
305 lines
11 KiB
C++
//===-- LanaiInstPrinter.cpp - Convert Lanai MCInst to asm syntax ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an Lanai MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "LanaiInstPrinter.h"
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#include "Lanai.h"
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#include "MCTargetDesc/LanaiMCExpr.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "LanaiGenAsmWriter.inc"
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void LanaiInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << StringRef(getRegisterName(RegNo)).lower();
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}
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bool LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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StringRef Alias, unsigned OpNo0,
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unsigned OpNo1) {
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OS << "\t" << Alias << " ";
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printOperand(MI, OpNo0, OS);
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OS << ", ";
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printOperand(MI, OpNo1, OS);
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return true;
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}
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static bool usesGivenOffset(const MCInst *MI, int AddOffset) {
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unsigned AluCode = MI->getOperand(3).getImm();
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return LPAC::encodeLanaiAluCode(AluCode) == LPAC::ADD &&
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(MI->getOperand(2).getImm() == AddOffset ||
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MI->getOperand(2).getImm() == -AddOffset);
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}
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static bool isPreIncrementForm(const MCInst *MI, int AddOffset) {
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unsigned AluCode = MI->getOperand(3).getImm();
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return LPAC::isPreOp(AluCode) && usesGivenOffset(MI, AddOffset);
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}
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static bool isPostIncrementForm(const MCInst *MI, int AddOffset) {
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unsigned AluCode = MI->getOperand(3).getImm();
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return LPAC::isPostOp(AluCode) && usesGivenOffset(MI, AddOffset);
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}
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static StringRef decIncOperator(const MCInst *MI) {
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if (MI->getOperand(2).getImm() < 0)
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return "--";
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return "++";
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}
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bool LanaiInstPrinter::printMemoryLoadIncrement(const MCInst *MI,
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raw_ostream &OS,
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StringRef Opcode,
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int AddOffset) {
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if (isPreIncrementForm(MI, AddOffset)) {
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OS << "\t" << Opcode << "\t[" << decIncOperator(MI) << "%"
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<< getRegisterName(MI->getOperand(1).getReg()) << "], %"
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<< getRegisterName(MI->getOperand(0).getReg());
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return true;
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}
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if (isPostIncrementForm(MI, AddOffset)) {
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OS << "\t" << Opcode << "\t[%"
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<< getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI)
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<< "], %" << getRegisterName(MI->getOperand(0).getReg());
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return true;
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}
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return false;
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}
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bool LanaiInstPrinter::printMemoryStoreIncrement(const MCInst *MI,
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raw_ostream &OS,
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StringRef Opcode,
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int AddOffset) {
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if (isPreIncrementForm(MI, AddOffset)) {
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OS << "\t" << Opcode << "\t%" << getRegisterName(MI->getOperand(0).getReg())
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<< ", [" << decIncOperator(MI) << "%"
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<< getRegisterName(MI->getOperand(1).getReg()) << "]";
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return true;
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}
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if (isPostIncrementForm(MI, AddOffset)) {
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OS << "\t" << Opcode << "\t%" << getRegisterName(MI->getOperand(0).getReg())
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<< ", [%" << getRegisterName(MI->getOperand(1).getReg())
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<< decIncOperator(MI) << "]";
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return true;
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}
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return false;
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}
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bool LanaiInstPrinter::printAlias(const MCInst *MI, raw_ostream &OS) {
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switch (MI->getOpcode()) {
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case Lanai::LDW_RI:
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// ld 4[*%rN], %rX => ld [++imm], %rX
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// ld -4[*%rN], %rX => ld [--imm], %rX
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// ld 4[%rN*], %rX => ld [imm++], %rX
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// ld -4[%rN*], %rX => ld [imm--], %rX
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return printMemoryLoadIncrement(MI, OS, "ld", 4);
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case Lanai::LDHs_RI:
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return printMemoryLoadIncrement(MI, OS, "ld.h", 2);
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case Lanai::LDHz_RI:
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return printMemoryLoadIncrement(MI, OS, "uld.h", 2);
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case Lanai::LDBs_RI:
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return printMemoryLoadIncrement(MI, OS, "ld.b", 1);
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case Lanai::LDBz_RI:
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return printMemoryLoadIncrement(MI, OS, "uld.b", 1);
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case Lanai::SW_RI:
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// st %rX, 4[*%rN] => st %rX, [++imm]
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// st %rX, -4[*%rN] => st %rX, [--imm]
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// st %rX, 4[%rN*] => st %rX, [imm++]
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// st %rX, -4[%rN*] => st %rX, [imm--]
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return printMemoryStoreIncrement(MI, OS, "st", 4);
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case Lanai::STH_RI:
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return printMemoryStoreIncrement(MI, OS, "st.h", 2);
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case Lanai::STB_RI:
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return printMemoryStoreIncrement(MI, OS, "st.b", 1);
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default:
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return false;
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}
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}
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void LanaiInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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StringRef Annotation,
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const MCSubtargetInfo & /*STI*/) {
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if (!printAlias(MI, OS) && !printAliasInstr(MI, OS))
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printInstruction(MI, OS);
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printAnnotation(OS, Annotation);
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}
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void LanaiInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS, const char *Modifier) {
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assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg())
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OS << "%" << getRegisterName(Op.getReg());
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else if (Op.isImm())
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OS << formatHex(Op.getImm());
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else {
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assert(Op.isExpr() && "Expected an expression");
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Op.getExpr()->print(OS, &MAI);
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}
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}
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void LanaiInstPrinter::printMemImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm()) {
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OS << '[' << formatHex(Op.getImm()) << ']';
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} else {
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// Symbolic operand will be lowered to immediate value by linker
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assert(Op.isExpr() && "Expected an expression");
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OS << '[';
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Op.getExpr()->print(OS, &MAI);
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OS << ']';
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}
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}
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void LanaiInstPrinter::printHi16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm()) {
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OS << formatHex(Op.getImm() << 16);
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} else {
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// Symbolic operand will be lowered to immediate value by linker
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assert(Op.isExpr() && "Expected an expression");
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Op.getExpr()->print(OS, &MAI);
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}
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}
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void LanaiInstPrinter::printHi16AndImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm()) {
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OS << formatHex((Op.getImm() << 16) | 0xffff);
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} else {
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// Symbolic operand will be lowered to immediate value by linker
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assert(Op.isExpr() && "Expected an expression");
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Op.getExpr()->print(OS, &MAI);
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}
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}
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void LanaiInstPrinter::printLo16AndImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm()) {
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OS << formatHex(0xffff0000 | Op.getImm());
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} else {
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// Symbolic operand will be lowered to immediate value by linker
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assert(Op.isExpr() && "Expected an expression");
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Op.getExpr()->print(OS, &MAI);
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}
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}
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static void printMemoryBaseRegister(raw_ostream &OS, const unsigned AluCode,
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const MCOperand &RegOp) {
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assert(RegOp.isReg() && "Register operand expected");
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OS << "[";
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if (LPAC::isPreOp(AluCode))
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OS << "*";
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OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg());
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if (LPAC::isPostOp(AluCode))
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OS << "*";
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OS << "]";
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}
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template <unsigned SizeInBits>
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static void printMemoryImmediateOffset(const MCAsmInfo &MAI,
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const MCOperand &OffsetOp,
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raw_ostream &OS) {
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assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected");
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if (OffsetOp.isImm()) {
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assert(isInt<SizeInBits>(OffsetOp.getImm()) && "Constant value truncated");
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OS << OffsetOp.getImm();
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} else
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OffsetOp.getExpr()->print(OS, &MAI);
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}
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void LanaiInstPrinter::printMemRiOperand(const MCInst *MI, int OpNo,
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raw_ostream &OS,
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const char * /*Modifier*/) {
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const MCOperand &RegOp = MI->getOperand(OpNo);
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const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
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const MCOperand &AluOp = MI->getOperand(OpNo + 2);
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const unsigned AluCode = AluOp.getImm();
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// Offset
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printMemoryImmediateOffset<16>(MAI, OffsetOp, OS);
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// Register
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printMemoryBaseRegister(OS, AluCode, RegOp);
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}
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void LanaiInstPrinter::printMemRrOperand(const MCInst *MI, int OpNo,
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raw_ostream &OS,
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const char * /*Modifier*/) {
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const MCOperand &RegOp = MI->getOperand(OpNo);
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const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
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const MCOperand &AluOp = MI->getOperand(OpNo + 2);
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const unsigned AluCode = AluOp.getImm();
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assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected.");
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// [ Base OP Offset ]
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OS << "[";
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if (LPAC::isPreOp(AluCode))
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OS << "*";
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OS << "%" << getRegisterName(RegOp.getReg());
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if (LPAC::isPostOp(AluCode))
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OS << "*";
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OS << " " << LPAC::lanaiAluCodeToString(AluCode) << " ";
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OS << "%" << getRegisterName(OffsetOp.getReg());
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OS << "]";
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}
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void LanaiInstPrinter::printMemSplsOperand(const MCInst *MI, int OpNo,
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raw_ostream &OS,
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const char * /*Modifier*/) {
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const MCOperand &RegOp = MI->getOperand(OpNo);
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const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
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const MCOperand &AluOp = MI->getOperand(OpNo + 2);
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const unsigned AluCode = AluOp.getImm();
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// Offset
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printMemoryImmediateOffset<10>(MAI, OffsetOp, OS);
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// Register
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printMemoryBaseRegister(OS, AluCode, RegOp);
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}
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void LanaiInstPrinter::printCCOperand(const MCInst *MI, int OpNo,
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raw_ostream &OS) {
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LPCC::CondCode CC =
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static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm());
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// Handle the undefined value here for printing so we don't abort().
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if (CC >= LPCC::UNKNOWN)
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OS << "<und>";
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else
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OS << lanaiCondCodeToString(CC);
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}
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void LanaiInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &OS) {
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LPCC::CondCode CC =
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static_cast<LPCC::CondCode>(MI->getOperand(OpNo).getImm());
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// Handle the undefined value here for printing so we don't abort().
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if (CC >= LPCC::UNKNOWN)
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OS << "<und>";
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else if (CC != LPCC::ICC_T)
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OS << "." << lanaiCondCodeToString(CC);
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}
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