2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
387 lines
12 KiB
C++
387 lines
12 KiB
C++
//===-- MSP430Disassembler.cpp - Disassembler for MSP430 ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MSP430Disassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430.h"
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#include "MCTargetDesc/MSP430MCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "msp430-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class MSP430Disassembler : public MCDisassembler {
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DecodeStatus getInstructionI(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const;
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DecodeStatus getInstructionII(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const;
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DecodeStatus getInstructionCJ(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const;
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public:
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MSP430Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createMSP430Disassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new MSP430Disassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeMSP430Disassembler() {
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TargetRegistry::RegisterMCDisassembler(getTheMSP430Target(),
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createMSP430Disassembler);
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}
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static const unsigned GR8DecoderTable[] = {
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MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB,
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MSP430::FPB, MSP430::R5B, MSP430::R6B, MSP430::R7B,
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MSP430::R8B, MSP430::R9B, MSP430::R10B, MSP430::R11B,
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MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B
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};
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static DecodeStatus DecodeGR8RegisterClass(MCInst &MI, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 15)
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return MCDisassembler::Fail;
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unsigned Reg = GR8DecoderTable[RegNo];
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MI.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static const unsigned GR16DecoderTable[] = {
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MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG,
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MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
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MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
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MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15
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};
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static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 15)
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return MCDisassembler::Fail;
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unsigned Reg = GR16DecoderTable[RegNo];
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MI.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
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uint64_t Address,
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const void *Decoder);
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#include "MSP430GenDisassemblerTables.inc"
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static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
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const void *Decoder) {
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int64_t Imm;
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switch (Bits) {
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default:
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llvm_unreachable("Invalid immediate value");
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case 0x22: Imm = 4; break;
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case 0x32: Imm = 8; break;
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case 0x03: Imm = 0; break;
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case 0x13: Imm = 1; break;
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case 0x23: Imm = 2; break;
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case 0x33: Imm = -1; break;
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}
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MI.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
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uint64_t Address,
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const void *Decoder) {
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unsigned Reg = Bits & 15;
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unsigned Imm = Bits >> 4;
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if (DecodeGR16RegisterClass(MI, Reg, Address, Decoder) !=
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MCDisassembler::Success)
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return MCDisassembler::Fail;
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MI.addOperand(MCOperand::createImm((int16_t)Imm));
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return MCDisassembler::Success;
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}
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enum AddrMode {
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amInvalid = 0,
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amRegister,
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amIndexed,
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amIndirect,
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amIndirectPost,
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amSymbolic,
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amImmediate,
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amAbsolute,
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amConstant
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};
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static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) {
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switch (Rs) {
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case 0:
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if (As == 1) return amSymbolic;
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if (As == 2) return amInvalid;
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if (As == 3) return amImmediate;
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break;
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case 2:
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if (As == 1) return amAbsolute;
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if (As == 2) return amConstant;
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if (As == 3) return amConstant;
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break;
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case 3:
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return amConstant;
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default:
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break;
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}
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switch (As) {
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case 0: return amRegister;
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case 1: return amIndexed;
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case 2: return amIndirect;
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case 3: return amIndirectPost;
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default:
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llvm_unreachable("As out of range");
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}
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}
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static AddrMode DecodeSrcAddrModeI(unsigned Insn) {
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unsigned Rs = fieldFromInstruction(Insn, 8, 4);
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unsigned As = fieldFromInstruction(Insn, 4, 2);
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return DecodeSrcAddrMode(Rs, As);
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}
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static AddrMode DecodeSrcAddrModeII(unsigned Insn) {
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unsigned Rs = fieldFromInstruction(Insn, 0, 4);
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unsigned As = fieldFromInstruction(Insn, 4, 2);
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return DecodeSrcAddrMode(Rs, As);
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}
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static AddrMode DecodeDstAddrMode(unsigned Insn) {
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unsigned Rd = fieldFromInstruction(Insn, 0, 4);
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unsigned Ad = fieldFromInstruction(Insn, 7, 1);
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switch (Rd) {
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case 0: return Ad ? amSymbolic : amRegister;
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case 2: return Ad ? amAbsolute : amRegister;
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default:
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break;
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}
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return Ad ? amIndexed : amRegister;
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}
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static const uint8_t *getDecoderTable(AddrMode SrcAM, unsigned Words) {
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assert(0 < Words && Words < 4 && "Incorrect number of words");
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switch (SrcAM) {
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default:
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llvm_unreachable("Invalid addressing mode");
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case amRegister:
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assert(Words < 3 && "Incorrect number of words");
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return Words == 2 ? DecoderTableAlpha32 : DecoderTableAlpha16;
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case amConstant:
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assert(Words < 3 && "Incorrect number of words");
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return Words == 2 ? DecoderTableBeta32 : DecoderTableBeta16;
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case amIndexed:
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case amSymbolic:
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case amImmediate:
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case amAbsolute:
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assert(Words > 1 && "Incorrect number of words");
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return Words == 2 ? DecoderTableGamma32 : DecoderTableGamma48;
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case amIndirect:
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case amIndirectPost:
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assert(Words < 3 && "Incorrect number of words");
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return Words == 2 ? DecoderTableDelta32 : DecoderTableDelta16;
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}
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}
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DecodeStatus MSP430Disassembler::getInstructionI(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const {
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uint64_t Insn = support::endian::read16le(Bytes.data());
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AddrMode SrcAM = DecodeSrcAddrModeI(Insn);
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AddrMode DstAM = DecodeDstAddrMode(Insn);
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if (SrcAM == amInvalid || DstAM == amInvalid) {
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Size = 2; // skip one word and let disassembler to try further
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return MCDisassembler::Fail;
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}
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unsigned Words = 1;
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switch (SrcAM) {
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case amIndexed:
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case amSymbolic:
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case amImmediate:
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case amAbsolute:
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if (Bytes.size() < (Words + 1) * 2) {
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Size = 2;
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return DecodeStatus::Fail;
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}
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Insn |= (uint64_t)support::endian::read16le(Bytes.data() + 2) << 16;
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++Words;
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break;
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default:
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break;
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}
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switch (DstAM) {
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case amIndexed:
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case amSymbolic:
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case amAbsolute:
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if (Bytes.size() < (Words + 1) * 2) {
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Size = 2;
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return DecodeStatus::Fail;
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}
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Insn |= (uint64_t)support::endian::read16le(Bytes.data() + Words * 2)
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<< (Words * 16);
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++Words;
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break;
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default:
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break;
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}
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DecodeStatus Result = decodeInstruction(getDecoderTable(SrcAM, Words), MI,
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Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = Words * 2;
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return Result;
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}
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Size = 2;
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return DecodeStatus::Fail;
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}
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DecodeStatus MSP430Disassembler::getInstructionII(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const {
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uint64_t Insn = support::endian::read16le(Bytes.data());
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AddrMode SrcAM = DecodeSrcAddrModeII(Insn);
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if (SrcAM == amInvalid) {
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Size = 2; // skip one word and let disassembler to try further
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return MCDisassembler::Fail;
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}
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unsigned Words = 1;
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switch (SrcAM) {
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case amIndexed:
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case amSymbolic:
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case amImmediate:
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case amAbsolute:
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if (Bytes.size() < (Words + 1) * 2) {
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Size = 2;
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return DecodeStatus::Fail;
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}
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Insn |= (uint64_t)support::endian::read16le(Bytes.data() + 2) << 16;
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++Words;
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break;
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default:
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break;
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}
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const uint8_t *DecoderTable = Words == 2 ? DecoderTable32 : DecoderTable16;
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DecodeStatus Result = decodeInstruction(DecoderTable, MI, Insn, Address,
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this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = Words * 2;
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return Result;
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}
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Size = 2;
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return DecodeStatus::Fail;
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}
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static MSP430CC::CondCodes getCondCode(unsigned Cond) {
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switch (Cond) {
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case 0: return MSP430CC::COND_NE;
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case 1: return MSP430CC::COND_E;
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case 2: return MSP430CC::COND_LO;
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case 3: return MSP430CC::COND_HS;
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case 4: return MSP430CC::COND_N;
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case 5: return MSP430CC::COND_GE;
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case 6: return MSP430CC::COND_L;
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case 7: return MSP430CC::COND_NONE;
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default:
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llvm_unreachable("Cond out of range");
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}
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}
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DecodeStatus MSP430Disassembler::getInstructionCJ(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const {
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uint64_t Insn = support::endian::read16le(Bytes.data());
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unsigned Cond = fieldFromInstruction(Insn, 10, 3);
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unsigned Offset = fieldFromInstruction(Insn, 0, 10);
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MI.addOperand(MCOperand::createImm(SignExtend32(Offset, 10)));
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if (Cond == 7)
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MI.setOpcode(MSP430::JMP);
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else {
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MI.setOpcode(MSP430::JCC);
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MI.addOperand(MCOperand::createImm(getCondCode(Cond)));
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}
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Size = 2;
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return DecodeStatus::Success;
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}
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DecodeStatus MSP430Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const {
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if (Bytes.size() < 2) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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uint64_t Insn = support::endian::read16le(Bytes.data());
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unsigned Opc = fieldFromInstruction(Insn, 13, 3);
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switch (Opc) {
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case 0:
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return getInstructionII(MI, Size, Bytes, Address, VStream, CStream);
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case 1:
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return getInstructionCJ(MI, Size, Bytes, Address, VStream, CStream);
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default:
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return getInstructionI(MI, Size, Bytes, Address, VStream, CStream);
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}
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}
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