2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
172 lines
5.2 KiB
TableGen
172 lines
5.2 KiB
TableGen
//===-- PPCInstrHTM.td - The PowerPC Hardware Transactional Memory -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hardware Transactional Memory extension to the
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// PowerPC instruction set.
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//
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//===----------------------------------------------------------------------===//
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def HasHTM : Predicate<"PPCSubTarget->hasHTM()">;
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def HTM_get_imm : SDNodeXForm<imm, [{
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return getI32Imm (N->getZExtValue(), SDLoc(N));
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}]>;
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let hasSideEffects = 1 in {
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def TCHECK_RET : PPCCustomInserterPseudo<(outs crrc:$out), (ins), "#TCHECK_RET", []>;
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}
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let Predicates = [HasHTM] in {
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def TBEGIN : XForm_htm0 <31, 654,
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(outs crrc0:$ret), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>;
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def TEND : XForm_htm1 <31, 686,
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(outs crrc0:$ret), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>;
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def TABORT : XForm_base_r3xo <31, 910,
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(outs crrc0:$ret), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR,
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[]>, isDOT {
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let RST = 0;
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let B = 0;
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}
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def TABORTWC : XForm_base_r3xo <31, 782,
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(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, gprc:$B),
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"tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>,
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isDOT;
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def TABORTWCI : XForm_base_r3xo <31, 846,
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(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
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"tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>,
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isDOT;
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def TABORTDC : XForm_base_r3xo <31, 814,
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(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, gprc:$B),
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"tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>,
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isDOT;
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def TABORTDCI : XForm_base_r3xo <31, 878,
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(outs crrc0:$ret), (ins u5imm:$RTS, gprc:$A, u5imm:$B),
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"tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>,
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isDOT;
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def TSR : XForm_htm2 <31, 750,
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(outs crrc0:$ret), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>,
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isDOT;
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def TCHECK : XForm_htm3 <31, 718,
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(outs), (ins crrc:$BF), "tcheck $BF", IIC_SprMTSPR, []>;
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def TRECLAIM : XForm_base_r3xo <31, 942,
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(outs crrc:$ret), (ins gprc:$A), "treclaim. $A",
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IIC_SprMTSPR, []>,
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isDOT {
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let RST = 0;
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let B = 0;
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}
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def TRECHKPT : XForm_base_r3xo <31, 1006,
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(outs crrc:$ret), (ins), "trechkpt.", IIC_SprMTSPR, []>,
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isDOT {
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let RST = 0;
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let A = 0;
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let B = 0;
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}
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// Builtins
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// All HTM instructions, with the exception of tcheck, set CR0 with the
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// value of the MSR Transaction State (TS) bits that exist before the
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// instruction is executed. For tbegin., the EQ bit in CR0 can be used
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// to determine whether the transaction was successfully started (0) or
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// failed (1). We use an XORI pattern to 'flip' the bit to match the
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// tbegin builtin API which defines a return value of 1 as success.
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def : Pat<(int_ppc_tbegin i32:$R),
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(XORI
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(EXTRACT_SUBREG (
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TBEGIN (HTM_get_imm imm:$R)), sub_eq),
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1)>;
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def : Pat<(int_ppc_tend i32:$R),
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(TEND (HTM_get_imm imm:$R))>;
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def : Pat<(int_ppc_tabort i32:$R),
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(TABORT $R)>;
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def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
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(TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>;
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def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
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(TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
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def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
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(TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>;
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def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
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(TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>;
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def : Pat<(int_ppc_tcheck),
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(TCHECK_RET)>;
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def : Pat<(int_ppc_treclaim i32:$RA),
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(TRECLAIM $RA)>;
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def : Pat<(int_ppc_trechkpt),
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(TRECHKPT)>;
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def : Pat<(int_ppc_tsr i32:$L),
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(TSR (HTM_get_imm imm:$L))>;
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def : Pat<(int_ppc_get_texasr),
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(MFSPR8 130)>;
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def : Pat<(int_ppc_get_texasru),
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(MFSPR8 131)>;
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def : Pat<(int_ppc_get_tfhar),
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(MFSPR8 128)>;
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def : Pat<(int_ppc_get_tfiar),
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(MFSPR8 129)>;
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def : Pat<(int_ppc_set_texasr i64:$V),
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(MTSPR8 130, $V)>;
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def : Pat<(int_ppc_set_texasru i64:$V),
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(MTSPR8 131, $V)>;
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def : Pat<(int_ppc_set_tfhar i64:$V),
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(MTSPR8 128, $V)>;
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def : Pat<(int_ppc_set_tfiar i64:$V),
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(MTSPR8 129, $V)>;
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// Extended mnemonics
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def : Pat<(int_ppc_tendall),
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(TEND 1)>;
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def : Pat<(int_ppc_tresume),
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(TSR 1)>;
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def : Pat<(int_ppc_tsuspend),
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(TSR 0)>;
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def : Pat<(i64 (int_ppc_ttest)),
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(RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>;
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} // [HasHTM]
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