e0bfeb5f24
Summary: Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models. This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between CMOV instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. This does complicate the scheduler models a little since we can't assign the A and BE instructions to a separate class now. I plan to make similar changes for SETcc and Jcc. Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet Reviewed By: RKSimon Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60041 llvm-svn: 357800
338 lines
12 KiB
C++
338 lines
12 KiB
C++
//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes common code for rendering MCInst instances as Intel-style
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// and Intel-style assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstPrinterCommon.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Casting.h"
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#include <cstdint>
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#include <cassert>
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using namespace llvm;
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void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm();
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switch (Imm) {
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default: llvm_unreachable("Invalid condcode argument!");
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case 0: O << "o"; break;
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case 1: O << "no"; break;
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case 2: O << "b"; break;
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case 3: O << "ae"; break;
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case 4: O << "e"; break;
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case 5: O << "ne"; break;
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case 6: O << "be"; break;
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case 7: O << "a"; break;
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case 8: O << "s"; break;
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case 9: O << "ns"; break;
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case 0xa: O << "p"; break;
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case 0xb: O << "np"; break;
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case 0xc: O << "l"; break;
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case 0xd: O << "ge"; break;
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case 0xe: O << "le"; break;
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case 0xf: O << "g"; break;
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}
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}
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void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm();
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switch (Imm) {
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default: llvm_unreachable("Invalid ssecc/avxcc argument!");
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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case 8: O << "eq_uq"; break;
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case 9: O << "nge"; break;
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case 0xa: O << "ngt"; break;
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case 0xb: O << "false"; break;
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case 0xc: O << "neq_oq"; break;
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case 0xd: O << "ge"; break;
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case 0xe: O << "gt"; break;
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case 0xf: O << "true"; break;
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case 0x10: O << "eq_os"; break;
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case 0x11: O << "lt_oq"; break;
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case 0x12: O << "le_oq"; break;
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case 0x13: O << "unord_s"; break;
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case 0x14: O << "neq_us"; break;
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case 0x15: O << "nlt_uq"; break;
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case 0x16: O << "nle_uq"; break;
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case 0x17: O << "ord_s"; break;
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case 0x18: O << "eq_us"; break;
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case 0x19: O << "nge_uq"; break;
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case 0x1a: O << "ngt_uq"; break;
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case 0x1b: O << "false_os"; break;
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case 0x1c: O << "neq_os"; break;
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case 0x1d: O << "ge_oq"; break;
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case 0x1e: O << "gt_oq"; break;
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case 0x1f: O << "true_us"; break;
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}
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}
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void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI,
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raw_ostream &OS) {
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OS << "vpcom";
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int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
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switch (Imm) {
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default: llvm_unreachable("Invalid vpcom argument!");
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case 0: OS << "lt"; break;
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case 1: OS << "le"; break;
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case 2: OS << "gt"; break;
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case 3: OS << "ge"; break;
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case 4: OS << "eq"; break;
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case 5: OS << "neq"; break;
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case 6: OS << "false"; break;
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case 7: OS << "true"; break;
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}
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Unexpected opcode!");
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case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break;
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case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break;
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case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break;
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case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break;
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case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break;
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case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break;
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case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break;
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case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break;
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}
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}
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void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI,
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raw_ostream &OS) {
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OS << "vpcmp";
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printSSEAVXCC(MI, MI->getNumOperands() - 1, OS);
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Unexpected opcode!");
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case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
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case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
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case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
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case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
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case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
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case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
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OS << "b\t";
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break;
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case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
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case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
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case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
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case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
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case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
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case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
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case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
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case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
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case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
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OS << "d\t";
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break;
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case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
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case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
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case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
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case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
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case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
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case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
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case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
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case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
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case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
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OS << "q\t";
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break;
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case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
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case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
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case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
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case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
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case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
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case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
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OS << "ub\t";
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break;
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case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
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case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
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case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
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case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
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case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
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case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
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case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
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case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
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case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
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OS << "ud\t";
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break;
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case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
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case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
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case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
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case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
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case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
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case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
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case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
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case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
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case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
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OS << "uq\t";
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break;
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case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
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case X86::VPCMPUWZ256rri: case X86::VPCMPUWZ256rmi:
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case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
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case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
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case X86::VPCMPUWZ256rrik: case X86::VPCMPUWZ256rmik:
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case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
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OS << "uw\t";
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break;
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case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
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case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
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case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
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case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
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case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
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case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
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OS << "w\t";
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break;
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}
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}
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void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp,
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raw_ostream &OS) {
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OS << (IsVCmp ? "vcmp" : "cmp");
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printSSEAVXCC(MI, MI->getNumOperands() - 1, OS);
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Unexpected opcode!");
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case X86::CMPPDrmi: case X86::CMPPDrri:
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case X86::VCMPPDrmi: case X86::VCMPPDrri:
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case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
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case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
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case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
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case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
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case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
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case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
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case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
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case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
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case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
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case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
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case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
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OS << "pd\t";
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break;
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case X86::CMPPSrmi: case X86::CMPPSrri:
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case X86::VCMPPSrmi: case X86::VCMPPSrri:
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case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
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case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
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case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
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case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
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case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
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case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
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case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
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case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
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case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
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case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
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case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
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OS << "ps\t";
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break;
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case X86::CMPSDrm: case X86::CMPSDrr:
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case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
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case X86::VCMPSDrm: case X86::VCMPSDrr:
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case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
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case X86::VCMPSDZrm: case X86::VCMPSDZrr:
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case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
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case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
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case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
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OS << "sd\t";
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break;
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case X86::CMPSSrm: case X86::CMPSSrr:
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case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
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case X86::VCMPSSrm: case X86::VCMPSSrr:
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case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
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case X86::VCMPSSZrm: case X86::VCMPSSZrr:
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case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
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case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
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case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
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OS << "ss\t";
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break;
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}
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}
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void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm();
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switch (Imm) {
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default:
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llvm_unreachable("Invalid rounding control!");
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case X86::TO_NEAREST_INT:
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O << "{rn-sae}";
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break;
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case X86::TO_NEG_INF:
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O << "{rd-sae}";
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break;
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case X86::TO_POS_INF:
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O << "{ru-sae}";
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break;
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case X86::TO_ZERO:
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O << "{rz-sae}";
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break;
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}
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}
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/// printPCRelImm - This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value (e.g. for jumps and calls). In
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/// Intel-style these print slightly differently than normal immediates.
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/// for example, a $ is not emitted.
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void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm())
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O << formatImm(Op.getImm());
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else {
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assert(Op.isExpr() && "unknown pcrel immediate operand");
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// If a symbolic branch target was added as a constant expression then print
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// that address in hex.
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const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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int64_t Address;
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if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
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O << formatHex((uint64_t)Address);
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} else {
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// Otherwise, just print the expression.
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Op.getExpr()->print(O, &MAI);
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}
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}
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}
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void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getReg()) {
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printOperand(MI, OpNo, O);
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O << ':';
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}
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}
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void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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uint64_t TSFlags = Desc.TSFlags;
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unsigned Flags = MI->getFlags();
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if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK))
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O << "\tlock\t";
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if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK))
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O << "\tnotrack\t";
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if (Flags & X86::IP_HAS_REPEAT_NE)
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O << "\trepne\t";
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else if (Flags & X86::IP_HAS_REPEAT)
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O << "\trep\t";
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}
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