36617f0160
Summary: This change is the first part of the AMDGPU target description
change. The aim of it is the effective splitting the vector and scalar
flows at the selection stage. Selection uses predicate functions based
on the framework implemented earlier - https://reviews.llvm.org/D35267
Differential revision: https://reviews.llvm.org/D52019
Reviewers: rampitec
llvm-svn: 342719
32 lines
1.8 KiB
LLVM
32 lines
1.8 KiB
LLVM
; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s
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; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE -check-prefix=HSA %s
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; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s
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; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA -check-prefix=HSA %s
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; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s
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; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; Make sure we don't overwrite workitem information with private memory
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; GCN-LABEL: {{^}}work_item_info:
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; GCN-NOT: v0
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; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v{{[0-9]+}}, v0
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
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entry:
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%0 = alloca [2 x i32], addrspace(5)
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%1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
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%2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
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store i32 0, i32 addrspace(5)* %1
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store i32 1, i32 addrspace(5)* %2
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%3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in
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%4 = load i32, i32 addrspace(5)* %3
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%5 = call i32 @llvm.amdgcn.workitem.id.x()
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%6 = add i32 %4, %5
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store i32 %6, i32 addrspace(1)* %out
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ret void
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}
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