fe59e14031
Summary: Nodes that have no uses are eventually pruned when they are selected from the worklist. Record nodes newly added to the worklist or DAG and perform pruning after every combine attempt. Reviewers: efriedma, RKSimon, craig.topper, spatel, jyknight Reviewed By: jyknight Subscribers: jdoerfert, jyknight, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58070 llvm-svn: 357283
293 lines
8.9 KiB
LLVM
293 lines
8.9 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; Make sure we don't crash or assert on spir_kernel calling convention.
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; GCN-LABEL: {{^}}kernel:
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; GCN: s_endpgm
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define spir_kernel void @kernel(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: This is treated like a kernel
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; XGCN-LABEL: {{^}}func:
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; XGCN: s_endpgm
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; define spir_func void @func(i32 addrspace(1)* %out) {
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; entry:
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; store i32 0, i32 addrspace(1)* %out
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; ret void
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; }
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; GCN-LABEL: {{^}}ps_ret_cc_f16:
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; SI: v_cvt_f16_f32_e32 v0, v0
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; SI: v_cvt_f32_f16_e32 v0, v0
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; SI: v_add_f32_e32 v0, 1.0, v0
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; VI: v_add_f16_e32 v0, 1.0, v0
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; VI: ; return
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define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16:
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; SI: v_cvt_f16_f32_e32 v0, s0
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; SI: v_cvt_f32_f16_e32 v0, v0
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; SI: v_add_f32_e32 v0, 1.0, v0
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; VI: v_add_f16_e64 v0, s0, 1.0
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; VI: ; return
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define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; GCN-LABEL: {{^}}fastcc:
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; GCN: v_add_f32_e32 v0, 4.0, v0
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define fastcc float @fastcc(float %arg0) #0 {
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%add = fadd float %arg0, 4.0
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ret float %add
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}
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; GCN-LABEL: {{^}}coldcc:
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; GCN: v_add_f32_e32 v0, 4.0, v0
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define coldcc float @coldcc(float %arg0) #0 {
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%add = fadd float %arg0, 4.0
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ret float %add
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}
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; GCN-LABEL: {{^}}call_coldcc:
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; GCN: v_mov_b32_e32 v0, 1.0
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; GCN: s_swappc_b64
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define amdgpu_kernel void @call_coldcc() #0 {
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%val = call float @coldcc(float 1.0)
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store float %val, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}call_fastcc:
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; GCN: v_mov_b32_e32 v0, 1.0
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; GCN: s_swappc_b64
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define amdgpu_kernel void @call_fastcc() #0 {
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%val = call float @fastcc(float 1.0)
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store float %val, float addrspace(1)* undef
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ret void
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}
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; Mesa compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 47176
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; GCN-LABEL: {{^}}cs_mesa:
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define amdgpu_cs half @cs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 45096
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; GCN-LABEL: {{^}}ps_mesa_f16:
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define amdgpu_ps half @ps_mesa_f16(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 45352
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; GCN-LABEL: {{^}}vs_mesa:
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define amdgpu_vs half @vs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa geometry shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 45608
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; GCN-LABEL: {{^}}gs_mesa:
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define amdgpu_gs half @gs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; Mesa hull shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config
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; GCN-LABEL: .AMDGPU.config
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; GCN: .long 46120
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; GCN-LABEL: {{^}}hs_mesa:
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define amdgpu_hs half @hs_mesa(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; FIXME: Inconsistent ABI between targets
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; GCN-LABEL: {{^}}ps_mesa_v2f16:
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; VI: v_mov_b32_e32 v1, 0x3c00
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; VI-NEXT: v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI-NEXT: v_add_f16_e32 v0, 1.0, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: ; return
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; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT0:v[0-9]+]], v0
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; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT1:v[0-9]+]], v1
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; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT0:v[0-9]+]], [[CVT_ELT0]]
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; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT1:v[0-9]+]], [[CVT_ELT1]]
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; SI-DAG: v_add_f32_e32 v0, 1.0, [[RECVT_ELT0]]
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; SI-DAG: v_add_f32_e32 v1, 1.0, [[RECVT_ELT1]]
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; SI: ; return to shader part epilog
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define amdgpu_ps <2 x half> @ps_mesa_v2f16(<2 x half> %arg0) {
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%add = fadd <2 x half> %arg0, <half 1.0, half 1.0>
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ret <2 x half> %add
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}
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; GCN-LABEL: {{^}}ps_mesa_inreg_v2f16:
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; VI: s_lshr_b32 s1, s0, 16
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; VI-NEXT: v_mov_b32_e32 v0, s1
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; VI-NEXT: v_mov_b32_e32 v1, 0x3c00
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; VI-NEXT: v_add_f16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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; VI-NEXT: v_add_f16_e64 v1, s0, 1.0
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; VI-NEXT: v_or_b32_e32 v0, v1, v0
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; VI-NEXT: ; return to shader part epilog
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; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT0:v[0-9]+]], s0
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; SI-DAG: v_cvt_f16_f32_e32 [[CVT_ELT1:v[0-9]+]], s1
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; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT0:v[0-9]+]], [[CVT_ELT0]]
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; SI-DAG: v_cvt_f32_f16_e32 [[RECVT_ELT1:v[0-9]+]], [[CVT_ELT1]]
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; SI-DAG: v_add_f32_e32 v0, 1.0, [[RECVT_ELT0]]
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; SI-DAG: v_add_f32_e32 v1, 1.0, [[RECVT_ELT1]]
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; SI: ; return to shader part epilog
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define amdgpu_ps <2 x half> @ps_mesa_inreg_v2f16(<2 x half> inreg %arg0) {
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%add = fadd <2 x half> %arg0, <half 1.0, half 1.0>
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ret <2 x half> %add
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}
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; GCN-LABEL: {{^}}ps_mesa_v2i16:
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; VI: v_mov_b32_e32 v2, 1
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; VI: v_add_u16_e32 v1, 1, v0
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; VI: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; VI: v_or_b32_e32 v0, v1, v0
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; SI: v_lshlrev_b32_e32 v1, 16, v1
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; SI: v_add_i32_e32 v0, vcc, 1, v0
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; SI: v_add_i32_e32 v1, vcc, 0x10000, v1
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; SI: v_and_b32
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; SI: v_or_b32
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define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) {
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%add = add <2 x i16> %arg0, <i16 1, i16 1>
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store <2 x i16> %add, <2 x i16> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_inreg_v2i16:
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; VI: s_and_b32 s1, s0, 0xffff0000
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; VI: s_add_i32 s0, s0, 1
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; VI: s_add_i32 s1, s1, 0x10000
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; VI: s_and_b32 s0, s0, 0xffff
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; VI: s_or_b32 s0, s0, s1
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; VI: v_mov_b32_e32 v0, s0
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; SI: s_lshl_b32 s1, s1, 16
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; SI: s_add_i32 s0, s0, 1
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; SI: s_add_i32 s1, s1, 0x10000
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; SI: s_and_b32 s0, s0, 0xffff
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; SI: s_or_b32 s0, s0, s1
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define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {
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%add = add <2 x i16> %arg0, <i16 1, i16 1>
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store <2 x i16> %add, <2 x i16> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_inreg_v3i32:
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; GCN-DAG: s_add_i32 s0, s0, 1
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; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2
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; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
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define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {
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%add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
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store <3 x i32> %add, <3 x i32> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_inreg_v3f32:
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; GCN-DAG: v_add_f32{{.*}}, s0, 1.0
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; GCN-DAG: v_add_f32{{.*}}, s1, 2.0
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; GCN-DAG: v_add_f32{{.*}}, s2, 4.0
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define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) {
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%add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
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store <3 x float> %add, <3 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_inreg_v5i32:
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; GCN-DAG: s_add_i32 s0, s0, 1
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; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2
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; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
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; GCN-DAG: s_add_i32 s{{[0-9]*}}, s3, 4
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; GCN-DAG: s_add_i32 s{{[0-9]*}}, s4, 5
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define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) {
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%add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
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store <5 x i32> %add, <5 x i32> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_inreg_v5f32:
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; GCN-DAG: v_add_f32{{.*}}, s0, 1.0
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; GCN-DAG: v_add_f32{{.*}}, s1, 2.0
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; GCN-DAG: v_add_f32{{.*}}, s2, 4.0
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; GCN-DAG: v_add_f32{{.*}}, s3, -1.0
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; GCN-DAG: v_add_f32{{.*}}, s4, 0.5
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define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) {
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%add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
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store <5 x float> %add, <5 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_v3i32:
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; GCN-DAG: v_add_{{.*}}, 1, v0
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; GCN-DAG: v_add_{{.*}}, 2, v1
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; GCN-DAG: v_add_{{.*}}, 3, v2
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define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) {
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%add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
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store <3 x i32> %add, <3 x i32> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_v3f32:
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; GCN-DAG: v_add_{{.*}}, 1.0, v0
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; GCN-DAG: v_add_{{.*}}, 2.0, v1
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; GCN-DAG: v_add_{{.*}}, 4.0, v2
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define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) {
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%add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
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store <3 x float> %add, <3 x float> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_v5i32:
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; GCN-DAG: v_add_{{.*}}, 1, v0
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; GCN-DAG: v_add_{{.*}}, 2, v1
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; GCN-DAG: v_add_{{.*}}, 3, v2
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; GCN-DAG: v_add_{{.*}}, 4, v3
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; GCN-DAG: v_add_{{.*}}, 5, v4
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define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) {
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%add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
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store <5 x i32> %add, <5 x i32> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}ps_mesa_v5f32:
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; GCN-DAG: v_add_f32{{.*}}, 1.0, v0
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; GCN-DAG: v_add_f32{{.*}}, 2.0, v1
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; GCN-DAG: v_add_f32{{.*}}, 4.0, v2
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; GCN-DAG: v_add_f32{{.*}}, -1.0, v3
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; GCN-DAG: v_add_f32{{.*}}, 0.5, v4
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define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {
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%add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
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store <5 x float> %add, <5 x float> addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind noinline }
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