4d47ac3b30
Also includes one example of how this transform is unsound. This isn't verifying the copies are used in the control flow intrinisic patterns. Also add option to disable exec mask opt pass. Since this pass is unsound, it may be useful to turn it off until it is fixed. llvm-svn: 357091
289 lines
11 KiB
LLVM
289 lines
11 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,ALL %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-opt-exec-mask-pre-ra=0 < %s | FileCheck -enable-var-scope -check-prefixes=DISABLED,ALL %s
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; ALL-LABEL: {{^}}simple_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF]]
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; GCN: s_and_b64 exec, exec, vcc
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; GCN-NEXT: ; mask branch [[ENDIF]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
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; GCN: ds_write_b32
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; GCN: s_endpgm
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; DISABLED: s_or_b64 exec, exec
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; DISABLED: s_or_b64 exec, exec
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define amdgpu_kernel void @simple_nested_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = icmp ugt i32 %tmp, 1
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br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.outer.end, label %bb.inner.then
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bb.inner.then: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 1
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%tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 1, i32 addrspace(1)* %tmp9, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb.outer.then, %bb.inner.then, %bb
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store i32 3, i32 addrspace(3)* null
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ret void
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}
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; ALL-LABEL: {{^}}uncollapsable_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_INNER:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_INNER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN: ds_write_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @uncollapsable_nested_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = icmp ugt i32 %tmp, 1
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br i1 %tmp1, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp4, align 4
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.inner.end, label %bb.inner.then
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bb.inner.then: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 1
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%tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 1, i32 addrspace(1)* %tmp8, align 4
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br label %bb.inner.end
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bb.inner.end: ; preds = %bb.inner.then, %bb.outer.then
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%tmp9 = add i32 %tmp, 2
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%tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp9
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store i32 2, i32 addrspace(1)* %tmp10, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb.inner.then, %bb
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store i32 3, i32 addrspace(3)* null
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ret void
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}
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; ALL-LABEL: {{^}}nested_if_if_else:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_xor_b64 [[SAVEEXEC_INNER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_INNER]]
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; GCN-NEXT: ; mask branch [[THEN_INNER:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[THEN_INNER]]:
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; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_INNER3:s\[[0-9:]+\]]], [[SAVEEXEC_INNER2]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_INNER3]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER]]
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN: ds_write_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @nested_if_if_else(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp1, align 4
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%tmp2 = icmp ugt i32 %tmp, 1
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br i1 %tmp2, label %bb.outer.then, label %bb.outer.end
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bb.outer.then: ; preds = %bb
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%tmp5 = icmp eq i32 %tmp, 2
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br i1 %tmp5, label %bb.then, label %bb.else
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bb.then: ; preds = %bb.outer.then
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%tmp3 = add i32 %tmp, 1
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp3
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store i32 1, i32 addrspace(1)* %tmp4, align 4
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br label %bb.outer.end
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bb.else: ; preds = %bb.outer.then
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%tmp7 = add i32 %tmp, 2
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%tmp9 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp7
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store i32 2, i32 addrspace(1)* %tmp9, align 4
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br label %bb.outer.end
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bb.outer.end: ; preds = %bb, %bb.then, %bb.else
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store i32 3, i32 addrspace(3)* null
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ret void
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}
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; ALL-LABEL: {{^}}nested_if_else_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: ; mask branch [[THEN_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[THEN_OUTER]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_ELSE:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[THEN_OUTER_FLOW:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[THEN_OUTER_FLOW]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
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; GCN-NEXT: {{^}}[[THEN_OUTER]]:
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; GCN-NEXT: s_or_saveexec_b64 [[SAVEEXEC_OUTER3:s\[[0-9:]+\]]], [[SAVEEXEC_OUTER2]]
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; GCN-NEXT: s_xor_b64 exec, exec, [[SAVEEXEC_OUTER3]]
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; GCN-NEXT: ; mask branch [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: s_and_saveexec_b64 [[SAVEEXEC_INNER_IF_OUTER_THEN:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[FLOW1:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: [[FLOW1]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_THEN]]
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN: ds_write_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @nested_if_else_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp1, align 4
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%cc1 = icmp ugt i32 %tmp, 1
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br i1 %cc1, label %bb.outer.then, label %bb.outer.else
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bb.outer.then:
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%tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 1
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store i32 1, i32 addrspace(1)* %tmp2, align 4
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%cc2 = icmp eq i32 %tmp, 2
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br i1 %cc2, label %bb.inner.then, label %bb.outer.end
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bb.inner.then:
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%tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 2
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store i32 2, i32 addrspace(1)* %tmp3, align 4
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br label %bb.outer.end
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bb.outer.else:
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 3
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store i32 3, i32 addrspace(1)* %tmp4, align 4
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%cc3 = icmp eq i32 %tmp, 2
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br i1 %cc3, label %bb.inner.then2, label %bb.outer.end
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bb.inner.then2:
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %tmp1, i32 4
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store i32 4, i32 addrspace(1)* %tmp5, align 4
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br label %bb.outer.end
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bb.outer.end:
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store i32 3, i32 addrspace(3)* null
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ret void
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}
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; ALL-LABEL: {{^}}s_endpgm_unsafe_barrier:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
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; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9_]+]]
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; GCN-NEXT: {{^BB[0-9_]+}}:
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; GCN: store_dword
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; GCN-NEXT: {{^}}[[ENDIF]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
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; GCN: s_barrier
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @s_endpgm_unsafe_barrier(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = icmp ugt i32 %tmp, 1
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br i1 %tmp1, label %bb.then, label %bb.end
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bb.then: ; preds = %bb
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%tmp4 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp
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store i32 0, i32 addrspace(1)* %tmp4, align 4
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br label %bb.end
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bb.end: ; preds = %bb.then, %bb
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call void @llvm.amdgcn.s.barrier()
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ret void
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}
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; Make sure scc liveness is updated if sor_b64 is removed
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; ALL-LABEL: {{^}}scc_liveness:
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; GCN: [[BB1_LOOP:BB[0-9]+_[0-9]+]]:
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; GCN: s_andn2_b64 exec, exec,
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; GCN-NEXT: s_cbranch_execnz [[BB1_LOOP]]
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; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen
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; GCN: s_and_b64 exec, exec, {{vcc|s\[[0-9:]+\]}}
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; GCN-NOT: s_or_b64 exec, exec
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; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
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; GCN: s_andn2_b64
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; GCN-NEXT: s_cbranch_execnz
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; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: s_setpc_b64
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define void @scc_liveness(i32 %arg) local_unnamed_addr #0 {
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bb:
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br label %bb1
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bb1: ; preds = %Flow1, %bb1, %bb
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%tmp = icmp slt i32 %arg, 519
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br i1 %tmp, label %bb2, label %bb1
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bb2: ; preds = %bb1
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%tmp3 = icmp eq i32 %arg, 0
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br i1 %tmp3, label %bb4, label %bb10
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bb4: ; preds = %bb2
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%tmp6 = load float, float addrspace(5)* undef
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%tmp7 = fcmp olt float %tmp6, 0.0
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br i1 %tmp7, label %bb8, label %Flow
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bb8: ; preds = %bb4
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%tmp9 = insertelement <4 x float> undef, float 0.0, i32 1
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br label %Flow
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Flow: ; preds = %bb8, %bb4
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%tmp8 = phi <4 x float> [ %tmp9, %bb8 ], [ zeroinitializer, %bb4 ]
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br label %bb10
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bb10: ; preds = %Flow, %bb2
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%tmp11 = phi <4 x float> [ zeroinitializer, %bb2 ], [ %tmp8, %Flow ]
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br i1 %tmp3, label %bb12, label %Flow1
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Flow1: ; preds = %bb10
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br label %bb1
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bb12: ; preds = %bb10
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store volatile <4 x float> %tmp11, <4 x float> addrspace(5)* undef, align 16
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare void @llvm.amdgcn.s.barrier() #1
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attributes #0 = { nounwind readnone speculatable }
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attributes #1 = { nounwind convergent }
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attributes #2 = { nounwind }
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