733b8571b4
The AMDGPU implementation of getReservedRegs depends on MachineFunctionInfo fields that are parsed from the YAML section. This was reserving the wrong register since it was setting the reserved regs before parsing the correct one. Some tests were relying on the default reserved set for the assumed default calling convention. llvm-svn: 357083
316 lines
8.4 KiB
YAML
316 lines
8.4 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: kill_all
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# GCN: bb.0:
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# GCN-NEXT: S_ENDPGM 0
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name: kill_all
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sgpr_32 }
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- { id: 4, class: sgpr_32 }
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%0 = IMPLICIT_DEF
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%3 = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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%1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
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%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
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%4 = S_ADD_U32 %3, 1, implicit-def $scc
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: load_without_memoperand
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr
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# GCN-NEXT: S_ENDPGM 0
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name: load_without_memoperand
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sgpr_32 }
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- { id: 4, class: sgpr_32 }
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%0 = IMPLICIT_DEF
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%3 = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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%1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
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%4 = S_ADD_U32 %3, 1, implicit-def $scc
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: load_volatile
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
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# GCN-NEXT: S_ENDPGM 0
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name: load_volatile
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sgpr_32 }
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- { id: 4, class: sgpr_32 }
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%0 = IMPLICIT_DEF
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%3 = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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%1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
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%2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
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%4 = S_ADD_U32 %3, 1, implicit-def $scc
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: store
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
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# GCN-NEXT: S_ENDPGM 0
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name: store
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64 }
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- { id: 1, class: vgpr_32 }
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: barrier
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: S_BARRIER
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# GCN-NEXT: S_ENDPGM 0
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name: barrier
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tracksRegLiveness: true
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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S_BARRIER
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: call
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
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# GCN-NEXT: S_ENDPGM 0
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name: call
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr2_sgpr3
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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$sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: exp
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: EXP 32, undef %0:vgpr_32, undef %1:vgpr_32, %2, undef %3:vgpr_32, 0, 0, 15, implicit $exec
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# GCN-NEXT: S_ENDPGM 0
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name: exp
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vgpr_32 }
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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EXP 32, undef %0, undef %1, killed %2, undef %3, 0, 0, 15, implicit $exec
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: return_to_epilog
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0
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name: return_to_epilog
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tracksRegLiveness: true
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$vgpr0 = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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SI_RETURN_TO_EPILOG killed $vgpr0
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...
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---
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# GCN-LABEL: name: split_block
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# GCN: bb.0:
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# GCN-NEXT: successors: %bb.1
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# GCN-NOT: S_OR_B64
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# GCN: bb.1:
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# GCN-NEXT: S_ENDPGM 0
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name: split_block
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: sgpr_32 }
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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bb.1:
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%0 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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%1 = V_ADD_F32_e64 0, killed %0, 0, 1, 0, 0, implicit $exec
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%3 = S_ADD_U32 %2, 1, implicit-def $scc
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: split_block_empty_block
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# GCN: bb.0:
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# GCN-NEXT: successors: %bb.1
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# GCN-NOT: S_OR_B64
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# GCN: bb.1:
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# GCN: bb.2:
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# GCN-NEXT: S_ENDPGM 0
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name: split_block_empty_block
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tracksRegLiveness: true
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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bb.1:
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bb.2:
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: split_block_uncond_branch
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# GCN: bb.0:
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# GCN-NEXT: successors: %bb.1
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# GCN: S_BRANCH %bb.1
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# GCN-NOT: S_OR_B64
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# GCN: bb.1:
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# GCN-NEXT: S_ENDPGM 0
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name: split_block_uncond_branch
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tracksRegLiveness: true
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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S_BRANCH %bb.1
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bb.1:
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: split_block_cond_branch
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# GCN: bb.0:
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# GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc
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# GCN: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
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# GCN: bb.1:
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# GCN: bb.2:
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# GCN-NEXT: S_ENDPGM 0
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name: split_block_cond_branch
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tracksRegLiveness: true
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc
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S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
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bb.1:
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bb.2:
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: two_preds_both_dead
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# GCN: bb.0:
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# GCN-NEXT: successors: %bb.2
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# GCN-NOT: S_OR
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# GCN: S_BRANCH %bb.2
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# GCN: bb.1:
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# GCN-NEXT: successors: %bb.2
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# GCN-NOT: S_AND
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# GCN: S_BRANCH %bb.2
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# GCN: bb.2:
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# GCN-NEXT: S_ENDPGM 0
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name: two_preds_both_dead
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tracksRegLiveness: true
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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S_BRANCH %bb.2
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bb.1:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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---
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# GCN-LABEL: name: two_preds_one_dead
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# GCN: bb.0:
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# GCN-NEXT: successors: %bb.2
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# GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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# GCN-NEXT: S_BARRIER
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# GCN-NEXT: S_BRANCH %bb.2
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# GCN: bb.1:
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# GCN-NEXT: successors: %bb.2
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# GCN-NOT: S_AND
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# GCN: S_BRANCH %bb.2
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# GCN: bb.2:
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# GCN-NEXT: S_ENDPGM 0
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name: two_preds_one_dead
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tracksRegLiveness: true
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body: |
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bb.0:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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S_BARRIER
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S_BRANCH %bb.2
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bb.1:
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN-LABEL: name: implicit_use_on_s_endpgm
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# GCN: V_ADD_I32
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# GCN: COPY
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# GCN: V_ADDC_U32
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# GCN: S_ENDPGM 0, implicit %3
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name: implicit_use_on_s_endpgm
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tracksRegLiveness: true
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body: |
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bb.0:
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dead %0:vgpr_32 = V_ADD_I32_e32 12345, undef %1:vgpr_32, implicit-def $vcc, implicit $exec
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%2:sreg_64_xexec = COPY $vcc
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%3:vgpr_32, dead %4:sreg_64_xexec = V_ADDC_U32_e64 undef %5:vgpr_32, undef %6:vgpr_32, %2, 0, implicit $exec
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S_ENDPGM 0, implicit %3
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...
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