20ea21c6ed
Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
33 lines
1005 B
YAML
33 lines
1005 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s
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--- |
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define amdgpu_kernel void @flags() {
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ret void
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}
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declare void @foo()
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...
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---
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name: flags
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liveins:
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- { reg: '$sgpr0_sgpr1' }
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frameInfo:
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maxAlignment: 8
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registers:
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- { id: 0, class: sreg_64, preferred-register: '' }
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- { id: 1, class: sreg_64, preferred-register: '' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: flags
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; CHECK: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
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; CHECK: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
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; CHECK: S_ENDPGM 0
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%0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead $scc
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%1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo
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S_ENDPGM 0
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...
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