5cf902ccd4
We have efficient codegen on P9 for lowering bswap that involves moving the value into a vector reg and moving it back. However, the check under which we custom lowered it did not adequately reflect the actual requirements. It required only that the subtarget be an implementation of ISA 3.0 since all compliant implementations have to provide the vector instructions. However, the kernel builds have a valid use case for -mno-altivec -mcpu=pwr9 (i.e. don't emit vector code, don't have to save vector regs for context switch). So we should require the correct features for this lowering. Fixes https://bugs.llvm.org/show_bug.cgi?id=39334 llvm-svn: 347376
38 lines
1.2 KiB
LLVM
38 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
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; RUN: -mcpu=pwr9 | FileCheck %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unkknown-unkknown \
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; RUN: -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=NO-ALTIVEC
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declare i64 @llvm.bswap.i64(i64)
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define i64 @bswap64(i64 %x) {
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; CHECK-LABEL: bswap64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mtvsrdd 34, 3, 3
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; CHECK-NEXT: xxbrd 0, 34
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; CHECK-NEXT: mfvsrd 3, 0
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; CHECK-NEXT: blr
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;
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; NO-ALTIVEC-LABEL: bswap64:
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; NO-ALTIVEC: # %bb.0: # %entry
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; NO-ALTIVEC-NEXT: rotldi 5, 3, 16
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; NO-ALTIVEC-NEXT: rotldi 4, 3, 8
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; NO-ALTIVEC-NEXT: rldimi 4, 5, 8, 48
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; NO-ALTIVEC-NEXT: rotldi 5, 3, 24
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; NO-ALTIVEC-NEXT: rldimi 4, 5, 16, 40
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; NO-ALTIVEC-NEXT: rotldi 5, 3, 32
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; NO-ALTIVEC-NEXT: rldimi 4, 5, 24, 32
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; NO-ALTIVEC-NEXT: rotldi 5, 3, 48
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; NO-ALTIVEC-NEXT: rldimi 4, 5, 40, 16
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; NO-ALTIVEC-NEXT: rotldi 5, 3, 56
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; NO-ALTIVEC-NEXT: rldimi 4, 5, 48, 8
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; NO-ALTIVEC-NEXT: rldimi 4, 3, 56, 0
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; NO-ALTIVEC-NEXT: mr 3, 4
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; NO-ALTIVEC-NEXT: blr
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entry:
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%0 = call i64 @llvm.bswap.i64(i64 %x)
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ret i64 %0
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}
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