80aa2290fb
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
508 lines
14 KiB
YAML
508 lines
14 KiB
YAML
# RUN: llc -mtriple=i386-unknown-unknown -mcpu=i486 %s -o - -run-pass greedy \
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# RUN: -debug-only=regalloc 2>&1 | FileCheck %s
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# REQUIRES: asserts
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--- |
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define void @fun() { ret void }
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declare noalias nonnull i8* @_Znwj()
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declare void @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_()
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declare zeroext i1 @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv()
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declare zeroext i1 @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv()
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...
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---
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# A physreg should always only be hinted once per getRegAllocationHints() query.
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# CHECK: hints: $ebx $edi
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# CHECK-NOT: hints: $ebx $edi $ebx $edi
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name: fun
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr32 }
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- { id: 1, class: gr32 }
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- { id: 2, class: gr32 }
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- { id: 3, class: gr32 }
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- { id: 4, class: gr32 }
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- { id: 5, class: gr32 }
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- { id: 6, class: gr32 }
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- { id: 7, class: gr32 }
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- { id: 8, class: gr32 }
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- { id: 9, class: gr32 }
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- { id: 10, class: gr32 }
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- { id: 11, class: gr32 }
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- { id: 12, class: gr32 }
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- { id: 13, class: gr32_abcd }
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- { id: 14, class: gr8 }
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- { id: 15, class: gr32_abcd }
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- { id: 16, class: gr8 }
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- { id: 17, class: gr32 }
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- { id: 18, class: gr32_abcd }
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- { id: 19, class: gr8 }
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- { id: 20, class: gr32_abcd }
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- { id: 21, class: gr8 }
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- { id: 22, class: gr32_abcd }
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- { id: 23, class: gr8 }
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- { id: 24, class: gr32_abcd }
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- { id: 25, class: gr8 }
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- { id: 26, class: gr32_abcd }
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- { id: 27, class: gr8 }
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- { id: 28, class: gr32_abcd }
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- { id: 29, class: gr8 }
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- { id: 30, class: gr32_abcd }
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- { id: 31, class: gr8 }
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- { id: 32, class: gr32_abcd }
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- { id: 33, class: gr8 }
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- { id: 34, class: gr32 }
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- { id: 35, class: gr32_abcd }
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- { id: 36, class: gr8 }
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- { id: 37, class: gr32 }
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- { id: 38, class: gr32 }
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- { id: 39, class: gr32_abcd }
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- { id: 40, class: gr8 }
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- { id: 41, class: gr32_abcd }
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- { id: 42, class: gr8 }
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- { id: 43, class: gr32_abcd }
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- { id: 44, class: gr8 }
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- { id: 45, class: gr32_abcd }
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- { id: 46, class: gr8 }
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- { id: 47, class: gr32_abcd }
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- { id: 48, class: gr8 }
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- { id: 49, class: gr8 }
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- { id: 50, class: gr32_abcd }
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- { id: 51, class: gr8 }
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- { id: 52, class: gr32 }
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- { id: 53, class: gr32 }
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- { id: 54, class: gr32 }
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- { id: 55, class: gr32 }
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- { id: 56, class: gr32_abcd }
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- { id: 57, class: gr8 }
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- { id: 58, class: gr32_abcd }
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- { id: 59, class: gr8 }
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- { id: 60, class: gr32_abcd }
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- { id: 61, class: gr8 }
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- { id: 62, class: gr32_abcd }
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- { id: 63, class: gr8 }
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- { id: 64, class: gr32_abcd }
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- { id: 65, class: gr8 }
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- { id: 66, class: gr32_abcd }
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- { id: 67, class: gr8 }
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- { id: 68, class: gr32_abcd }
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- { id: 69, class: gr8 }
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- { id: 70, class: gr32_abcd }
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- { id: 71, class: gr8 }
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- { id: 72, class: gr32_abcd }
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- { id: 73, class: gr8 }
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- { id: 74, class: gr32 }
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- { id: 75, class: gr32 }
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- { id: 76, class: gr32_abcd }
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- { id: 77, class: gr8 }
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- { id: 78, class: gr32_abcd }
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- { id: 79, class: gr32 }
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- { id: 80, class: gr32 }
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- { id: 81, class: gr32_abcd }
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- { id: 82, class: gr32 }
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frameInfo:
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maxAlignment: 4
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hasCalls: true
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fixedStack:
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- { id: 0, size: 4, alignment: 4, stack-id: 0, isImmutable: true }
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body: |
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bb.0:
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successors: %bb.1(0x00000001), %bb.2(0x7fffffff)
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%13:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %13.sub_8bit, %13.sub_8bit, implicit-def $eflags
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JCC_1 %bb.2, 5, implicit killed $eflags
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JMP_1 %bb.1
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bb.1:
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successors:
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bb.2:
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successors: %bb.4(0x7fffffff), %bb.3(0x00000001)
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%15:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %15.sub_8bit, %15.sub_8bit, implicit-def $eflags
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JCC_1 %bb.4, 5, implicit killed $eflags
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JMP_1 %bb.3
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bb.3:
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successors:
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bb.4:
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successors: %bb.6(0x7fffffff), %bb.5(0x00000001)
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%12:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg
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%1:gr32 = LEA32r %12, 1, $noreg, 144, $noreg
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MOV32mr undef %17:gr32, 1, $noreg, 0, $noreg, %1
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%18:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %18.sub_8bit, %18.sub_8bit, implicit-def $eflags
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JCC_1 %bb.6, 5, implicit killed $eflags
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JMP_1 %bb.5
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bb.5:
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successors:
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bb.6:
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successors: %bb.7(0x00000001), %bb.8(0x7fffffff)
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%20:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %20.sub_8bit, %20.sub_8bit, implicit-def $eflags
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JCC_1 %bb.8, 5, implicit killed $eflags
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JMP_1 %bb.7
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bb.7:
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successors:
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bb.8:
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successors: %bb.10(0x7fffffff), %bb.9(0x00000001)
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%22:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %22.sub_8bit, %22.sub_8bit, implicit-def $eflags
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JCC_1 %bb.10, 5, implicit killed $eflags
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JMP_1 %bb.9
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bb.9:
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successors:
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bb.10:
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successors: %bb.12(0x7fffffff), %bb.11(0x00000001)
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%24:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %24.sub_8bit, %24.sub_8bit, implicit-def $eflags
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JCC_1 %bb.12, 5, implicit killed $eflags
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JMP_1 %bb.11
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bb.11:
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successors:
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bb.12:
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successors: %bb.13(0x00000001), %bb.14(0x7fffffff)
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%26:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %26.sub_8bit, %26.sub_8bit, implicit-def $eflags
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JCC_1 %bb.14, 5, implicit killed $eflags
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JMP_1 %bb.13
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bb.13:
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successors:
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bb.14:
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%0:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
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%28:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %28.sub_8bit, %28.sub_8bit, implicit-def $eflags
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JCC_1 %bb.20, 5, implicit killed $eflags
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JMP_1 %bb.15
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bb.15:
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successors: %bb.16(0x00000001), %bb.17(0x7fffffff)
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%78:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
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JCC_1 %bb.17, 5, implicit killed $eflags
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JMP_1 %bb.16
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bb.16:
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successors:
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bb.17:
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successors: %bb.18(0x7fffffff), %bb.19(0x00000001)
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TEST8rr %78.sub_8bit, %78.sub_8bit, implicit-def $eflags
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JCC_1 %bb.19, 4, implicit killed $eflags
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bb.18:
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%79:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
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JMP_1 %bb.21
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bb.19:
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successors:
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bb.20:
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%78:gr32_abcd = COPY %0
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%79:gr32 = COPY %0
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bb.21:
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successors: %bb.22, %bb.23
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%35:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %35.sub_8bit, %35.sub_8bit, implicit-def $eflags
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%80:gr32 = IMPLICIT_DEF
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JCC_1 %bb.23, 5, implicit killed $eflags
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JMP_1 %bb.22
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bb.22:
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ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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CALLpcrel32 @_Znwj, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax
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ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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%80:gr32 = COPY killed $eax
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MOV32mr undef %38:gr32, 1, $noreg, 0, $noreg, %78
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MOV32mr %79, 1, $noreg, 0, $noreg, %80
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ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
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ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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bb.23:
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successors: %bb.24(0x00000001), %bb.25(0x7fffffff)
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MOV32mi %80, 1, $noreg, 52, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private15_preEnd__authorEv
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%39:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %39.sub_8bit, %39.sub_8bit, implicit-def $eflags
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JCC_1 %bb.25, 5, implicit killed $eflags
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JMP_1 %bb.24
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bb.24:
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successors:
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bb.25:
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successors: %bb.27(0x7fffffff), %bb.26(0x00000001)
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%41:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %41.sub_8bit, %41.sub_8bit, implicit-def $eflags
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JCC_1 %bb.27, 5, implicit killed $eflags
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JMP_1 %bb.26
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bb.26:
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successors:
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bb.27:
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successors: %bb.29(0x7fffffff), %bb.28(0x00000001)
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%43:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %43.sub_8bit, %43.sub_8bit, implicit-def $eflags
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JCC_1 %bb.29, 5, implicit killed $eflags
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JMP_1 %bb.28
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bb.28:
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successors:
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bb.29:
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successors: %bb.31(0x7fffffff), %bb.30(0x00000001)
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%45:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %45.sub_8bit, %45.sub_8bit, implicit-def $eflags
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JCC_1 %bb.31, 5, implicit killed $eflags
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JMP_1 %bb.30
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bb.30:
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successors:
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bb.31:
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successors: %bb.32(0x00000001), %bb.33(0x7fffffff)
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%47:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %47.sub_8bit, %47.sub_8bit, implicit-def $eflags
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JCC_1 %bb.33, 5, implicit killed $eflags
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JMP_1 %bb.32
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bb.32:
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successors:
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bb.33:
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successors: %bb.37(0x30000000), %bb.34(0x50000000)
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%49:gr8 = MOV8ri 1
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TEST8rr %49, %49, implicit-def $eflags
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JCC_1 %bb.37, 5, implicit killed $eflags
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JMP_1 %bb.34
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bb.34:
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successors: %bb.36(0x00000001), %bb.35(0x7fffffff)
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%81:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %81.sub_8bit, %81.sub_8bit, implicit-def $eflags
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JCC_1 %bb.36, 4, implicit killed $eflags
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bb.35:
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%82:gr32 = LEA32r %12, 1, $noreg, 80, $noreg
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JMP_1 %bb.38
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bb.36:
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successors:
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bb.37:
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%81:gr32_abcd = COPY %0
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%82:gr32 = COPY %0
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bb.38:
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successors: %bb.40(0x7fffffff), %bb.39(0x00000001)
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ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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CALLpcrel32 @_Znwj, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp, implicit-def $eax
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ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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%52:gr32 = COPY killed $eax
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MOV32mr undef %53:gr32, 1, $noreg, 0, $noreg, %81
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MOV32mr %82, 1, $noreg, 0, $noreg, %52
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ADJCALLSTACKDOWN32 0, 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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CALLpcrel32 @_ZNSt3__127__tree_balance_after_insertIPNS_16__tree_node_baseIPvEEEEvT_S5_, csr_32, implicit $esp, implicit $ssp, implicit-def $esp, implicit-def $ssp
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ADJCALLSTACKUP32 0, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp
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MOV32mi %52, 1, $noreg, 36, $noreg, @_ZN15COLLADASaxFWL1429ColladaParserAutoGen14Private14_end__commentsEv
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MOV32mr undef %54:gr32, 1, $noreg, 0, $noreg, %1
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%55:gr32 = MOV32rm %12, 1, $noreg, 140, $noreg
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CMP32mi8 %55, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
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JCC_1 %bb.40, 4, implicit killed $eflags
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JMP_1 %bb.39
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bb.39:
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successors:
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bb.40:
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successors: %bb.42(0x00000001), %bb.41(0x7fffffff)
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%56:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %56.sub_8bit, %56.sub_8bit, implicit-def $eflags
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JCC_1 %bb.42, 5, implicit killed $eflags
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JMP_1 %bb.41
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bb.41:
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successors: %bb.43(0x00000001), %bb.44(0x7fffffff)
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%58:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %58.sub_8bit, %58.sub_8bit, implicit-def $eflags
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JCC_1 %bb.43, 5, implicit killed $eflags
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JMP_1 %bb.44
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bb.42:
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successors:
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bb.43:
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successors:
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bb.44:
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successors: %bb.45(0x00000001), %bb.46(0x7fffffff)
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%60:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %60.sub_8bit, %60.sub_8bit, implicit-def $eflags
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JCC_1 %bb.46, 5, implicit killed $eflags
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JMP_1 %bb.45
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bb.45:
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successors:
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bb.46:
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successors: %bb.48(0x7fffffff), %bb.47(0x00000001)
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%62:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %62.sub_8bit, %62.sub_8bit, implicit-def $eflags
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JCC_1 %bb.48, 5, implicit killed $eflags
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JMP_1 %bb.47
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bb.47:
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successors:
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bb.48:
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successors: %bb.50(0x7fffffff), %bb.49(0x00000001)
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%64:gr32_abcd = MOV32r0 implicit-def dead $eflags
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TEST8rr %64.sub_8bit, %64.sub_8bit, implicit-def $eflags
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JCC_1 %bb.50, 5, implicit killed $eflags
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JMP_1 %bb.49
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bb.49:
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successors:
|
|
|
|
|
|
bb.50:
|
|
successors: %bb.51(0x00000001), %bb.52(0x7fffffff)
|
|
|
|
%66:gr32_abcd = MOV32r0 implicit-def dead $eflags
|
|
TEST8rr %66.sub_8bit, %66.sub_8bit, implicit-def $eflags
|
|
JCC_1 %bb.52, 5, implicit killed $eflags
|
|
JMP_1 %bb.51
|
|
|
|
bb.51:
|
|
successors:
|
|
|
|
|
|
bb.52:
|
|
successors: %bb.54(0x7fffffff), %bb.53(0x00000001)
|
|
|
|
%68:gr32_abcd = MOV32r0 implicit-def dead $eflags
|
|
TEST8rr %68.sub_8bit, %68.sub_8bit, implicit-def $eflags
|
|
JCC_1 %bb.54, 5, implicit killed $eflags
|
|
JMP_1 %bb.53
|
|
|
|
bb.53:
|
|
successors:
|
|
|
|
|
|
bb.54:
|
|
successors: %bb.55(0x00000001), %bb.56(0x7fffffff)
|
|
|
|
%70:gr32_abcd = MOV32r0 implicit-def dead $eflags
|
|
TEST8rr %70.sub_8bit, %70.sub_8bit, implicit-def $eflags
|
|
JCC_1 %bb.56, 5, implicit killed $eflags
|
|
JMP_1 %bb.55
|
|
|
|
bb.55:
|
|
successors:
|
|
|
|
|
|
bb.56:
|
|
successors: %bb.57(0x00000001), %bb.58(0x7fffffff)
|
|
|
|
%72:gr32_abcd = MOV32r0 implicit-def dead $eflags
|
|
TEST8rr %72.sub_8bit, %72.sub_8bit, implicit-def $eflags
|
|
JCC_1 %bb.58, 5, implicit killed $eflags
|
|
JMP_1 %bb.57
|
|
|
|
bb.57:
|
|
successors:
|
|
|
|
|
|
bb.58:
|
|
successors: %bb.62(0x00000001), %bb.59(0x7fffffff)
|
|
|
|
CMP32mi8 %0, 1, $noreg, 0, $noreg, 0, implicit-def $eflags
|
|
JCC_1 %bb.62, 4, implicit killed $eflags
|
|
JMP_1 %bb.59
|
|
|
|
bb.59:
|
|
|
|
bb.60:
|
|
successors: %bb.60(0x7fffffff), %bb.61(0x00000001)
|
|
|
|
CMP32ri undef %75:gr32, 95406325, implicit-def $eflags
|
|
JCC_1 %bb.61, 2, implicit killed $eflags
|
|
JMP_1 %bb.60
|
|
|
|
bb.61:
|
|
successors:
|
|
|
|
|
|
bb.62:
|
|
successors: %bb.63, %bb.64
|
|
|
|
%76:gr32_abcd = MOV32r0 implicit-def dead $eflags
|
|
TEST8rr %76.sub_8bit, %76.sub_8bit, implicit-def $eflags
|
|
JCC_1 %bb.64, 5, implicit killed $eflags
|
|
JMP_1 %bb.63
|
|
|
|
bb.63:
|
|
successors:
|
|
|
|
|
|
bb.64:
|
|
|
|
...
|