153 lines
4.9 KiB
LLVM
153 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard < %s | FileCheck %s --check-prefix=CHECKHARD
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; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft < %s | FileCheck %s --check-prefix=CHECKSOFT
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define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_lane_f16_1:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vmovx.f16 s0, s0
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; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_lane_f16_1:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vmovx.f16 s0, s0
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; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s0
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <4 x half> %a, i32 1
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_lane_f16_2:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s1
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_lane_f16_2:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s1
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <4 x half> %a, i32 2
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_laneq_f16_6:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s3
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_laneq_f16_6:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s3
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <8 x half> %a, i32 6
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_laneq_f16_7:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vmovx.f16 s0, s3
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; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_laneq_f16_7:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vmovx.f16 s0, s3
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; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s0
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <8 x half> %a, i32 7
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%conv = fpext half %elt to float
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ret float %conv
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}
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define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_lane_f16:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f16.f32 s2, s2
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; CHECKHARD-NEXT: vmov.f16 r0, s2
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; CHECKHARD-NEXT: vmov.16 d0[3], r0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_lane_f16:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov s0, r2
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; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECKSOFT-NEXT: vmov d16, r0, r1
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; CHECKSOFT-NEXT: vmov.f16 r2, s0
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; CHECKSOFT-NEXT: vmov.16 d16[3], r2
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; CHECKSOFT-NEXT: vmov r0, r1, d16
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <4 x half> %a, half %b, i32 3
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ret <4 x half> %x
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}
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define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_laneq_f16_1:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4
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; CHECKHARD-NEXT: vmov.f16 r0, s4
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; CHECKHARD-NEXT: vmov.16 d0[1], r0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_laneq_f16_1:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vldr s0, [sp]
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; CHECKSOFT-NEXT: vmov d17, r2, r3
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; CHECKSOFT-NEXT: vmov d16, r0, r1
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; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECKSOFT-NEXT: vmov.f16 r12, s0
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; CHECKSOFT-NEXT: vmov.16 d16[1], r12
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; CHECKSOFT-NEXT: vmov r2, r3, d17
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; CHECKSOFT-NEXT: vmov r0, r1, d16
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <8 x half> %a, half %b, i32 1
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ret <8 x half> %x
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}
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define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_laneq_f16_7:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4
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; CHECKHARD-NEXT: vmov.f16 r0, s4
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; CHECKHARD-NEXT: vmov.16 d1[3], r0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_laneq_f16_7:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vldr s0, [sp]
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; CHECKSOFT-NEXT: vmov d17, r2, r3
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; CHECKSOFT-NEXT: vmov d16, r0, r1
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; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
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; CHECKSOFT-NEXT: vmov.f16 r12, s0
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; CHECKSOFT-NEXT: vmov.16 d17[3], r12
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; CHECKSOFT-NEXT: vmov r0, r1, d16
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; CHECKSOFT-NEXT: vmov r2, r3, d17
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <8 x half> %a, half %b, i32 7
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ret <8 x half> %x
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}
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