fdc4ea34e3
This patch aims to reduce spilling and register moves by using the 3-address versions of instructions per default instead of the 2-address equivalent ones. It seems that both spilling and register moves are improved noticeably generally. Regalloc hints are passed to increase conversions to 2-address instructions which are done in SystemZShortenInst.cpp (after regalloc). Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are the same), foldMemoryOperandImpl() can no longer trivially fold a spilled source register since the reg/reg instruction is now 3-address. In order to remedy this, new 3-address pseudo memory instructions are used to perform the folding only when the dst and lhs virtual registers are known to be allocated to the same physreg. In order to not let MachineCopyPropagation run and change registers on these transformed instructions (making it 3-address), a new target pass called SystemZPostRewrite.cpp is run just after VirtRegRewriter, that immediately lowers the pseudo to a target instruction. If it would have been possibe to insert a COPY instruction and change a register operand (convert to 2-address) in foldMemoryOperandImpl() while trusting that the caller (e.g. InlineSpiller) would update/repair the involved LiveIntervals, the solution involving pseudo instructions would not have been needed. This is perhaps a potential improvement (see Phabricator post). Common code changes: * A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a target pass immediately before MachineCopyPropagation. * VirtRegMap is passed as an argument to foldMemoryOperand(). Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D60888 llvm-svn: 362868
202 lines
8.2 KiB
C++
202 lines
8.2 KiB
C++
//==- SystemZ.h - Top-Level Interface for SystemZ representation -*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in
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// the LLVM SystemZ backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZ_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZ_H
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class SystemZTargetMachine;
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class FunctionPass;
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namespace SystemZ {
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// Condition-code mask values.
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const unsigned CCMASK_0 = 1 << 3;
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const unsigned CCMASK_1 = 1 << 2;
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const unsigned CCMASK_2 = 1 << 1;
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const unsigned CCMASK_3 = 1 << 0;
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const unsigned CCMASK_ANY = CCMASK_0 | CCMASK_1 | CCMASK_2 | CCMASK_3;
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// Condition-code mask assignments for integer and floating-point
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// comparisons.
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const unsigned CCMASK_CMP_EQ = CCMASK_0;
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const unsigned CCMASK_CMP_LT = CCMASK_1;
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const unsigned CCMASK_CMP_GT = CCMASK_2;
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const unsigned CCMASK_CMP_NE = CCMASK_CMP_LT | CCMASK_CMP_GT;
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const unsigned CCMASK_CMP_LE = CCMASK_CMP_EQ | CCMASK_CMP_LT;
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const unsigned CCMASK_CMP_GE = CCMASK_CMP_EQ | CCMASK_CMP_GT;
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// Condition-code mask assignments for floating-point comparisons only.
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const unsigned CCMASK_CMP_UO = CCMASK_3;
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const unsigned CCMASK_CMP_O = CCMASK_ANY ^ CCMASK_CMP_UO;
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// All condition-code values produced by comparisons.
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const unsigned CCMASK_ICMP = CCMASK_0 | CCMASK_1 | CCMASK_2;
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const unsigned CCMASK_FCMP = CCMASK_0 | CCMASK_1 | CCMASK_2 | CCMASK_3;
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// Condition-code mask assignments for arithmetical operations.
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const unsigned CCMASK_ARITH_EQ = CCMASK_0;
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const unsigned CCMASK_ARITH_LT = CCMASK_1;
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const unsigned CCMASK_ARITH_GT = CCMASK_2;
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const unsigned CCMASK_ARITH_OVERFLOW = CCMASK_3;
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const unsigned CCMASK_ARITH = CCMASK_ANY;
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// Condition-code mask assignments for logical operations.
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const unsigned CCMASK_LOGICAL_ZERO = CCMASK_0 | CCMASK_2;
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const unsigned CCMASK_LOGICAL_NONZERO = CCMASK_1 | CCMASK_2;
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const unsigned CCMASK_LOGICAL_CARRY = CCMASK_2 | CCMASK_3;
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const unsigned CCMASK_LOGICAL_NOCARRY = CCMASK_0 | CCMASK_1;
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const unsigned CCMASK_LOGICAL_BORROW = CCMASK_LOGICAL_NOCARRY;
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const unsigned CCMASK_LOGICAL_NOBORROW = CCMASK_LOGICAL_CARRY;
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const unsigned CCMASK_LOGICAL = CCMASK_ANY;
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// Condition-code mask assignments for CS.
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const unsigned CCMASK_CS_EQ = CCMASK_0;
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const unsigned CCMASK_CS_NE = CCMASK_1;
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const unsigned CCMASK_CS = CCMASK_0 | CCMASK_1;
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// Condition-code mask assignments for a completed SRST loop.
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const unsigned CCMASK_SRST_FOUND = CCMASK_1;
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const unsigned CCMASK_SRST_NOTFOUND = CCMASK_2;
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const unsigned CCMASK_SRST = CCMASK_1 | CCMASK_2;
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// Condition-code mask assignments for TEST UNDER MASK.
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const unsigned CCMASK_TM_ALL_0 = CCMASK_0;
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const unsigned CCMASK_TM_MIXED_MSB_0 = CCMASK_1;
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const unsigned CCMASK_TM_MIXED_MSB_1 = CCMASK_2;
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const unsigned CCMASK_TM_ALL_1 = CCMASK_3;
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const unsigned CCMASK_TM_SOME_0 = CCMASK_TM_ALL_1 ^ CCMASK_ANY;
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const unsigned CCMASK_TM_SOME_1 = CCMASK_TM_ALL_0 ^ CCMASK_ANY;
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const unsigned CCMASK_TM_MSB_0 = CCMASK_0 | CCMASK_1;
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const unsigned CCMASK_TM_MSB_1 = CCMASK_2 | CCMASK_3;
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const unsigned CCMASK_TM = CCMASK_ANY;
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// Condition-code mask assignments for TRANSACTION_BEGIN.
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const unsigned CCMASK_TBEGIN_STARTED = CCMASK_0;
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const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1;
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const unsigned CCMASK_TBEGIN_TRANSIENT = CCMASK_2;
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const unsigned CCMASK_TBEGIN_PERSISTENT = CCMASK_3;
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const unsigned CCMASK_TBEGIN = CCMASK_ANY;
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// Condition-code mask assignments for TRANSACTION_END.
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const unsigned CCMASK_TEND_TX = CCMASK_0;
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const unsigned CCMASK_TEND_NOTX = CCMASK_2;
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const unsigned CCMASK_TEND = CCMASK_TEND_TX | CCMASK_TEND_NOTX;
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// Condition-code mask assignments for vector comparisons (and similar
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// operations).
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const unsigned CCMASK_VCMP_ALL = CCMASK_0;
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const unsigned CCMASK_VCMP_MIXED = CCMASK_1;
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const unsigned CCMASK_VCMP_NONE = CCMASK_3;
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const unsigned CCMASK_VCMP = CCMASK_0 | CCMASK_1 | CCMASK_3;
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// Condition-code mask assignments for Test Data Class.
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const unsigned CCMASK_TDC_NOMATCH = CCMASK_0;
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const unsigned CCMASK_TDC_MATCH = CCMASK_1;
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const unsigned CCMASK_TDC = CCMASK_TDC_NOMATCH | CCMASK_TDC_MATCH;
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// The position of the low CC bit in an IPM result.
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const unsigned IPM_CC = 28;
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// Mask assignments for PFD.
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const unsigned PFD_READ = 1;
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const unsigned PFD_WRITE = 2;
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// Mask assignments for TDC
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const unsigned TDCMASK_ZERO_PLUS = 0x800;
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const unsigned TDCMASK_ZERO_MINUS = 0x400;
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const unsigned TDCMASK_NORMAL_PLUS = 0x200;
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const unsigned TDCMASK_NORMAL_MINUS = 0x100;
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const unsigned TDCMASK_SUBNORMAL_PLUS = 0x080;
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const unsigned TDCMASK_SUBNORMAL_MINUS = 0x040;
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const unsigned TDCMASK_INFINITY_PLUS = 0x020;
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const unsigned TDCMASK_INFINITY_MINUS = 0x010;
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const unsigned TDCMASK_QNAN_PLUS = 0x008;
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const unsigned TDCMASK_QNAN_MINUS = 0x004;
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const unsigned TDCMASK_SNAN_PLUS = 0x002;
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const unsigned TDCMASK_SNAN_MINUS = 0x001;
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const unsigned TDCMASK_ZERO = TDCMASK_ZERO_PLUS | TDCMASK_ZERO_MINUS;
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const unsigned TDCMASK_POSITIVE = TDCMASK_NORMAL_PLUS |
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TDCMASK_SUBNORMAL_PLUS |
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TDCMASK_INFINITY_PLUS;
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const unsigned TDCMASK_NEGATIVE = TDCMASK_NORMAL_MINUS |
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TDCMASK_SUBNORMAL_MINUS |
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TDCMASK_INFINITY_MINUS;
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const unsigned TDCMASK_NAN = TDCMASK_QNAN_PLUS |
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TDCMASK_QNAN_MINUS |
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TDCMASK_SNAN_PLUS |
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TDCMASK_SNAN_MINUS;
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const unsigned TDCMASK_PLUS = TDCMASK_POSITIVE |
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TDCMASK_ZERO_PLUS |
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TDCMASK_QNAN_PLUS |
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TDCMASK_SNAN_PLUS;
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const unsigned TDCMASK_MINUS = TDCMASK_NEGATIVE |
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TDCMASK_ZERO_MINUS |
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TDCMASK_QNAN_MINUS |
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TDCMASK_SNAN_MINUS;
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const unsigned TDCMASK_ALL = TDCMASK_PLUS | TDCMASK_MINUS;
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// Number of bits in a vector register.
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const unsigned VectorBits = 128;
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// Number of bytes in a vector register (and consequently the number of
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// bytes in a general permute vector).
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const unsigned VectorBytes = VectorBits / 8;
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// Return true if Val fits an LLILL operand.
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static inline bool isImmLL(uint64_t Val) {
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return (Val & ~0x000000000000ffffULL) == 0;
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}
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// Return true if Val fits an LLILH operand.
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static inline bool isImmLH(uint64_t Val) {
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return (Val & ~0x00000000ffff0000ULL) == 0;
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}
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// Return true if Val fits an LLIHL operand.
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static inline bool isImmHL(uint64_t Val) {
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return (Val & ~0x00000ffff00000000ULL) == 0;
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}
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// Return true if Val fits an LLIHH operand.
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static inline bool isImmHH(uint64_t Val) {
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return (Val & ~0xffff000000000000ULL) == 0;
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}
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// Return true if Val fits an LLILF operand.
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static inline bool isImmLF(uint64_t Val) {
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return (Val & ~0x00000000ffffffffULL) == 0;
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}
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// Return true if Val fits an LLIHF operand.
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static inline bool isImmHF(uint64_t Val) {
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return (Val & ~0xffffffff00000000ULL) == 0;
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}
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} // end namespace SystemZ
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FunctionPass *createSystemZISelDag(SystemZTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createSystemZElimComparePass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZExpandPseudoPass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZShortenInstPass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZLongBranchPass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZLDCleanupPass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM);
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FunctionPass *createSystemZTDCPass();
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} // end namespace llvm
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#endif
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