37bd9bd137
"Divergence driven ISel. Assign register class for cross block values
according to the divergence."
that discovered the design flaw leading to several issues that
required to be solved before.
This change reverts AMDGPU specific changes and keeps common part
unaffected.
llvm-svn: 362749
162 lines
6.2 KiB
LLVM
162 lines
6.2 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Make sure to test with f32 and i32 compares. If we have to use float
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; compares, we always have multiple condition registers. If we can do
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; scalar compares, we don't want to use multiple condition registers.
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; GCN-LABEL: {{^}}opt_select_i32_and_cmp_i32:
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; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN-NOT: [[RESULT]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @opt_select_i32_and_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 {
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%icmp0 = icmp ne i32 %a, %b
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%icmp1 = icmp ne i32 %a, %c
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%and = and i1 %icmp0, %icmp1
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%select = select i1 %and, i32 %x, i32 %y
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store i32 %select, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}opt_select_i32_and_cmp_f32:
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; GCN-DAG: v_cmp_lg_f32_e32 vcc
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; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN-NOT: [[RESULT]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @opt_select_i32_and_cmp_f32(i32 addrspace(1)* %out, float %a, float %b, float %c, i32 %x, i32 %y) #0 {
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%fcmp0 = fcmp one float %a, %b
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%fcmp1 = fcmp one float %a, %c
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%and = and i1 %fcmp0, %fcmp1
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%select = select i1 %and, i32 %x, i32 %y
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store i32 %select, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}opt_select_i64_and_cmp_i32:
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; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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define amdgpu_kernel void @opt_select_i64_and_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
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%icmp0 = icmp ne i32 %a, %b
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%icmp1 = icmp ne i32 %a, %c
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%and = and i1 %icmp0, %icmp1
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%select = select i1 %and, i64 %x, i64 %y
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store i64 %select, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}opt_select_i64_and_cmp_f32:
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; GCN-DAG: v_cmp_lg_f32_e32 vcc,
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; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_and_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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define amdgpu_kernel void @opt_select_i64_and_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 {
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%fcmp0 = fcmp one float %a, %b
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%fcmp1 = fcmp one float %a, %c
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%and = and i1 %fcmp0, %fcmp1
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%select = select i1 %and, i64 %x, i64 %y
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store i64 %select, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}opt_select_i32_or_cmp_i32:
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; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN-NOT: [[RESULT]]
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; GCN: buffer_store_dword [[RESULT]]
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; GCN: s_endpgm
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define amdgpu_kernel void @opt_select_i32_or_cmp_i32(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %x, i32 %y) #0 {
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%icmp0 = icmp ne i32 %a, %b
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%icmp1 = icmp ne i32 %a, %c
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%or = or i1 %icmp0, %icmp1
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%select = select i1 %or, i32 %x, i32 %y
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store i32 %select, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}opt_select_i32_or_cmp_f32:
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; GCN-DAG: v_cmp_lg_f32_e32 vcc
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; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN-NOT: [[RESULT]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @opt_select_i32_or_cmp_f32(i32 addrspace(1)* %out, float %a, float %b, float %c, i32 %x, i32 %y) #0 {
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%fcmp0 = fcmp one float %a, %b
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%fcmp1 = fcmp one float %a, %c
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%or = or i1 %fcmp0, %fcmp1
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%select = select i1 %or, i32 %x, i32 %y
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store i32 %select, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}opt_select_i64_or_cmp_i32:
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; GCN-DAG: v_cmp_ne_u32_e32 vcc,
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; GCN-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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define amdgpu_kernel void @opt_select_i64_or_cmp_i32(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i64 %x, i64 %y) #0 {
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%icmp0 = icmp ne i32 %a, %b
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%icmp1 = icmp ne i32 %a, %c
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%or = or i1 %icmp0, %icmp1
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%select = select i1 %or, i64 %x, i64 %y
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store i64 %select, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}opt_select_i64_or_cmp_f32:
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; GCN-DAG: v_cmp_lg_f32_e32 vcc,
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; GCN-DAG: v_cmp_lg_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]]
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; GCN: s_or_b64 vcc, vcc, [[CMP1]]
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; GCN: v_cndmask_b32_e32 v[[RESULT1:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: v_cndmask_b32_e32 v[[RESULT0:[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, vcc
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; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT0]]:[[RESULT1]]{{\]}}
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define amdgpu_kernel void @opt_select_i64_or_cmp_f32(i64 addrspace(1)* %out, float %a, float %b, float %c, i64 %x, i64 %y) #0 {
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%fcmp0 = fcmp one float %a, %b
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%fcmp1 = fcmp one float %a, %c
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%or = or i1 %fcmp0, %fcmp1
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%select = select i1 %or, i64 %x, i64 %y
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store i64 %select, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}regression:
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; GCN: v_cmp_neq_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 1.0
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; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}}
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; GCN: v_cmp_eq_f32_e32 vcc, 0, v{{[0-9]+}}
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define amdgpu_kernel void @regression(float addrspace(1)* %out, float %c0, float %c1) #0 {
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entry:
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%cmp0 = fcmp oeq float %c0, 1.0
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br i1 %cmp0, label %if0, label %endif
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if0:
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%cmp1 = fcmp oeq float %c1, 0.0
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br i1 %cmp1, label %if1, label %endif
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if1:
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%cmp2 = xor i1 %cmp1, true
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br label %endif
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endif:
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%tmp0 = phi i1 [ true, %entry ], [ %cmp2, %if1 ], [ false, %if0 ]
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%tmp2 = select i1 %tmp0, float 4.0, float 0.0
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store float %tmp2, float addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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