0ceda9fb5c
This is something of a workaround, and the state of stack realignment controls is kind of a mess. Ideally, we would be able to specify the stack is infinitely aligned on entry to a kernel. TargetFrameLowering provides multiple controls which apply at different points. The StackRealignable field is used during SelectionDAG, and for some reason distinct from this hook. StackAlignment is a single field not dependent on the function. It would probably be better to make that dependent on the calling convention, and the maximum value for kernels. Currently this doesn't really change anything, since the frame lowering mostly does its own thing. This helps avoid regressions in a future change which will rely more heavily on hasFP. llvm-svn: 362447
295 lines
13 KiB
LLVM
295 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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; Make sure the stack is never realigned for entry functions.
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define amdgpu_kernel void @max_alignment_128() #0 {
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; VI-LABEL: max_alignment_128:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_u32 s4, s4, s7
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; VI-NEXT: v_mov_b32_e32 v0, 9
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; VI-NEXT: s_mov_b32 flat_scratch_lo, s5
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; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], s7 offset:128
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; VI-NEXT: s_endpgm
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; VI-NEXT: .section .rodata,#alloc
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; VI-NEXT: .p2align 6
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; VI-NEXT: .amdhsa_kernel max_alignment_128
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; VI-NEXT: .amdhsa_group_segment_fixed_size 0
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; VI-NEXT: .amdhsa_private_segment_fixed_size 256
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; VI-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; VI-NEXT: .amdhsa_next_free_vgpr 1
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; VI-NEXT: .amdhsa_next_free_sgpr 8
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; VI-NEXT: .amdhsa_reserve_vcc 0
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; VI-NEXT: .amdhsa_float_round_mode_32 0
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; VI-NEXT: .amdhsa_float_round_mode_16_64 0
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; VI-NEXT: .amdhsa_float_denorm_mode_32 0
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; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; VI-NEXT: .amdhsa_dx10_clamp 1
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; VI-NEXT: .amdhsa_ieee_mode 1
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; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; VI-NEXT: .amdhsa_exception_fp_denorm_src 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; VI-NEXT: .amdhsa_exception_int_div_zero 0
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; VI-NEXT: .end_amdhsa_kernel
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; VI-NEXT: .text
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;
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; GFX9-LABEL: max_alignment_128:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
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; GFX9-NEXT: v_mov_b32_e32 v0, 9
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s7 offset:128
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .section .rodata,#alloc
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; GFX9-NEXT: .p2align 6
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; GFX9-NEXT: .amdhsa_kernel max_alignment_128
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; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
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; GFX9-NEXT: .amdhsa_private_segment_fixed_size 256
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GFX9-NEXT: .amdhsa_next_free_vgpr 1
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; GFX9-NEXT: .amdhsa_next_free_sgpr 8
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; GFX9-NEXT: .amdhsa_reserve_vcc 0
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; GFX9-NEXT: .amdhsa_float_round_mode_32 0
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; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_32 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; GFX9-NEXT: .amdhsa_dx10_clamp 1
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; GFX9-NEXT: .amdhsa_ieee_mode 1
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; GFX9-NEXT: .amdhsa_fp16_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; GFX9-NEXT: .amdhsa_exception_int_div_zero 0
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; GFX9-NEXT: .end_amdhsa_kernel
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; GFX9-NEXT: .text
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%alloca.align = alloca i32, align 128, addrspace(5)
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store volatile i32 9, i32 addrspace(5)* %alloca.align, align 128
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ret void
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}
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define amdgpu_kernel void @stackrealign_attr() #1 {
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; VI-LABEL: stackrealign_attr:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_u32 s4, s4, s7
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; VI-NEXT: v_mov_b32_e32 v0, 9
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; VI-NEXT: s_mov_b32 flat_scratch_lo, s5
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; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], s7 offset:4
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; VI-NEXT: s_endpgm
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; VI-NEXT: .section .rodata,#alloc
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; VI-NEXT: .p2align 6
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; VI-NEXT: .amdhsa_kernel stackrealign_attr
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; VI-NEXT: .amdhsa_group_segment_fixed_size 0
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; VI-NEXT: .amdhsa_private_segment_fixed_size 8
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; VI-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; VI-NEXT: .amdhsa_next_free_vgpr 1
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; VI-NEXT: .amdhsa_next_free_sgpr 8
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; VI-NEXT: .amdhsa_reserve_vcc 0
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; VI-NEXT: .amdhsa_float_round_mode_32 0
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; VI-NEXT: .amdhsa_float_round_mode_16_64 0
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; VI-NEXT: .amdhsa_float_denorm_mode_32 0
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; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; VI-NEXT: .amdhsa_dx10_clamp 1
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; VI-NEXT: .amdhsa_ieee_mode 1
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; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; VI-NEXT: .amdhsa_exception_fp_denorm_src 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; VI-NEXT: .amdhsa_exception_int_div_zero 0
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; VI-NEXT: .end_amdhsa_kernel
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; VI-NEXT: .text
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;
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; GFX9-LABEL: stackrealign_attr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
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; GFX9-NEXT: v_mov_b32_e32 v0, 9
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s7 offset:4
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .section .rodata,#alloc
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; GFX9-NEXT: .p2align 6
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; GFX9-NEXT: .amdhsa_kernel stackrealign_attr
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; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
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; GFX9-NEXT: .amdhsa_private_segment_fixed_size 8
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GFX9-NEXT: .amdhsa_next_free_vgpr 1
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; GFX9-NEXT: .amdhsa_next_free_sgpr 8
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; GFX9-NEXT: .amdhsa_reserve_vcc 0
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; GFX9-NEXT: .amdhsa_float_round_mode_32 0
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; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_32 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; GFX9-NEXT: .amdhsa_dx10_clamp 1
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; GFX9-NEXT: .amdhsa_ieee_mode 1
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; GFX9-NEXT: .amdhsa_fp16_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; GFX9-NEXT: .amdhsa_exception_int_div_zero 0
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; GFX9-NEXT: .end_amdhsa_kernel
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; GFX9-NEXT: .text
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%alloca.align = alloca i32, align 4, addrspace(5)
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store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
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ret void
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}
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define amdgpu_kernel void @alignstack_attr() #2 {
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; VI-LABEL: alignstack_attr:
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; VI: ; %bb.0:
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; VI-NEXT: s_add_u32 s4, s4, s7
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; VI-NEXT: v_mov_b32_e32 v0, 9
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; VI-NEXT: s_mov_b32 flat_scratch_lo, s5
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; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], s7 offset:4
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; VI-NEXT: s_endpgm
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; VI-NEXT: .section .rodata,#alloc
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; VI-NEXT: .p2align 6
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; VI-NEXT: .amdhsa_kernel alignstack_attr
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; VI-NEXT: .amdhsa_group_segment_fixed_size 0
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; VI-NEXT: .amdhsa_private_segment_fixed_size 128
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; VI-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; VI-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; VI-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; VI-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; VI-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; VI-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; VI-NEXT: .amdhsa_next_free_vgpr 1
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; VI-NEXT: .amdhsa_next_free_sgpr 8
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; VI-NEXT: .amdhsa_reserve_vcc 0
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; VI-NEXT: .amdhsa_float_round_mode_32 0
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; VI-NEXT: .amdhsa_float_round_mode_16_64 0
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; VI-NEXT: .amdhsa_float_denorm_mode_32 0
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; VI-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; VI-NEXT: .amdhsa_dx10_clamp 1
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; VI-NEXT: .amdhsa_ieee_mode 1
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; VI-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; VI-NEXT: .amdhsa_exception_fp_denorm_src 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; VI-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; VI-NEXT: .amdhsa_exception_int_div_zero 0
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; VI-NEXT: .end_amdhsa_kernel
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; VI-NEXT: .text
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;
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; GFX9-LABEL: alignstack_attr:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
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; GFX9-NEXT: v_mov_b32_e32 v0, 9
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s7 offset:4
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; GFX9-NEXT: s_endpgm
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; GFX9-NEXT: .section .rodata,#alloc
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; GFX9-NEXT: .p2align 6
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; GFX9-NEXT: .amdhsa_kernel alignstack_attr
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; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
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; GFX9-NEXT: .amdhsa_private_segment_fixed_size 128
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_queue_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 0
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; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_id 0
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; GFX9-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
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; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_size 0
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; GFX9-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_y 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_id_z 0
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; GFX9-NEXT: .amdhsa_system_sgpr_workgroup_info 0
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; GFX9-NEXT: .amdhsa_system_vgpr_workitem_id 0
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; GFX9-NEXT: .amdhsa_next_free_vgpr 1
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; GFX9-NEXT: .amdhsa_next_free_sgpr 8
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; GFX9-NEXT: .amdhsa_reserve_vcc 0
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; GFX9-NEXT: .amdhsa_float_round_mode_32 0
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; GFX9-NEXT: .amdhsa_float_round_mode_16_64 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_32 0
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; GFX9-NEXT: .amdhsa_float_denorm_mode_16_64 3
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; GFX9-NEXT: .amdhsa_dx10_clamp 1
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; GFX9-NEXT: .amdhsa_ieee_mode 1
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; GFX9-NEXT: .amdhsa_fp16_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_invalid_op 0
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; GFX9-NEXT: .amdhsa_exception_fp_denorm_src 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_div_zero 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_overflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_underflow 0
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; GFX9-NEXT: .amdhsa_exception_fp_ieee_inexact 0
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; GFX9-NEXT: .amdhsa_exception_int_div_zero 0
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; GFX9-NEXT: .end_amdhsa_kernel
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; GFX9-NEXT: .text
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%alloca.align = alloca i32, align 4, addrspace(5)
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store volatile i32 9, i32 addrspace(5)* %alloca.align, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind "stackrealign" }
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attributes #2 = { nounwind alignstack=128 }
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